452 lines
15 KiB
C
452 lines
15 KiB
C
/* $NetBSD: instr.h,v 1.5 2000/08/16 11:33:27 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)instr.h 8.1 (Berkeley) 6/11/93
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*/
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/* see also Appendix F of the SPARC version 8 document */
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enum IOP { IOP_OP2, IOP_CALL, IOP_reg, IOP_mem };
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enum IOP2 { IOP2_UNIMP, IOP2_BPcc, IOP2_Bicc, IOP2_BPr,
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IOP2_SETHI, IOP2_FBPfcc, IOP2_FBfcc, IOP2_CBccc };
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enum IOP3_reg {
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IOP3_ADD, IOP3_AND, IOP3_OR, IOP3_XOR,
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IOP3_SUB, IOP3_ANDN, IOP3_ORN, IOP3_XNOR,
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IOP3_ADDX, IOP3_rerr09, IOP3_UMUL, IOP3_SMUL,
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IOP3_SUBX, IOP3_rerr0d, IOP3_UDIV, IOP3_SDIV,
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IOP3_ADDcc, IOP3_ANDcc, IOP3_ORcc, IOP3_XORcc,
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IOP3_SUBcc, IOP3_ANDNcc, IOP3_ORNcc, IOP3_XNORcc,
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IOP3_ADDXcc, IOP3_rerr19, IOP3_UMULcc, IOP3_SMULcc,
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IOP3_SUBXcc, IOP3_rerr1d, IOP3_UDIVcc, IOP3_SDIVcc,
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IOP3_TADDcc, IOP3_TSUBcc, IOP3_TADDccTV, IOP3_TSUBccTV,
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IOP3_MULScc, IOP3_SLL, IOP3_SRL, IOP3_SRA,
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IOP3_RDASR_RDY_STBAR, IOP3_RDPSR, IOP3_RDWIM, IOP3_RDTGBR,
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IOP3_rerr2c, IOP3_rerr2d, IOP3_rerr2e, IOP3_rerr2f,
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IOP3_WRASR_WRY, IOP3_WRPSR, IOP3_WRWIM, IOP3_WRTBR,
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IOP3_FPop1, IOP3_FPop2, IOP3_CPop1, IOP3_CPop2,
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IOP3_JMPL, IOP3_RETT, IOP3_Ticc, IOP3_FLUSH,
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IOP3_SAVE, IOP3_RESTORE, IOP3_rerr3e, IOP3_rerr3f
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};
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enum IOP3_mem {
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IOP3_LD, IOP3_LDUB, IOP3_LDUH, IOP3_LDD,
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IOP3_ST, IOP3_STB, IOP3_STH, IOP3_STD,
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IOP3_merr08, IOP3_LDSB, IOP3_LDSH, IOP3_merr0b,
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IOP3_merr0c, IOP3_LDSTUB, IOP3_merr0f, IOP3_SWAP,
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IOP3_LDA, IOP3_LDUBA, IOP3_LDUHA, IOP3_LDDA,
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IOP3_STA, IOP3_STBA, IOP3_STHA, IOP3_STDA,
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IOP3_merr18, IOP3_LDSBA, IOP3_LDSHA, IOP3_merr1b,
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IOP3_merr1c, IOP3_LDSTUBA, IOP3_merr1f, IOP3_SWAPA,
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IOP3_LDF, IOP3_LDFSR, IOP3_merr22, IOP3_LDDF,
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IOP3_STF, IOP3_STFSR, IOP3_STDFQ, IOP3_STDF,
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IOP3_merr28, IOP3_merr29, IOP3_merr2a, IOP3_merr2b,
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IOP3_merr2c, IOP3_merr2d, IOP3_merr2e, IOP3_merr2f,
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IOP3_LFC, IOP3_LDCSR, IOP3_merr32, IOP3_LDDC,
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IOP3_STC, IOP3_STCSR, IOP3_STDCQ, IOP3_STDC,
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IOP3_merr38, IOP3_merr39, IOP3_merr3a, IOP3_merr3b,
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IOP3_merr3c, IOP3_merr3d, IOP3_merr3e, IOP3_merr3f
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};
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/*
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* Integer condition codes.
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*/
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#define Icc_N 0x0 /* never */
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#define Icc_E 0x1 /* equal (equiv. zero) */
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#define Icc_LE 0x2 /* less or equal */
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#define Icc_L 0x3 /* less */
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#define Icc_LEU 0x4 /* less or equal unsigned */
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#define Icc_CS 0x5 /* carry set (equiv. less unsigned) */
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#define Icc_NEG 0x6 /* negative */
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#define Icc_VS 0x7 /* overflow set */
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#define Icc_A 0x8 /* always */
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#define Icc_NE 0x9 /* not equal (equiv. not zero) */
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#define Icc_G 0xa /* greater */
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#define Icc_GE 0xb /* greater or equal */
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#define Icc_GU 0xc /* greater unsigned */
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#define Icc_CC 0xd /* carry clear (equiv. gtr or eq unsigned) */
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#define Icc_POS 0xe /* positive */
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#define Icc_VC 0xf /* overflow clear */
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/*
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* Integer registers.
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*/
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#define I_G0 0
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#define I_G1 1
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#define I_G2 2
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#define I_G3 3
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#define I_G4 4
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#define I_G5 5
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#define I_G6 6
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#define I_G7 7
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#define I_O0 8
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#define I_O1 9
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#define I_O2 10
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#define I_O3 11
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#define I_O4 12
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#define I_O5 13
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#define I_O6 14
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#define I_O7 15
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#define I_L0 16
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#define I_L1 17
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#define I_L2 18
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#define I_L3 19
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#define I_L4 20
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#define I_L5 21
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#define I_L6 22
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#define I_L7 23
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#define I_I0 24
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#define I_I1 25
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#define I_I2 26
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#define I_I3 27
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#define I_I4 28
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#define I_I5 29
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#define I_I6 30
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#define I_I7 31
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/*
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* An instruction.
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*/
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union instr {
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int i_int; /* as a whole */
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/*
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* The first level of decoding is to use the top 2 bits.
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* This gives us one of three `formats', which usually give
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* a second level of decoding.
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*/
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struct {
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u_int i_op:2; /* first-level decode */
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u_int :30;
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} i_any;
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/*
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* Format 1 instructions: CALL (undifferentiated).
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*/
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struct {
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u_int :2; /* 01 */
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int i_disp:30; /* displacement */
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} i_call;
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/*
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* Format 2 instructions (SETHI, UNIMP, and branches, plus illegal
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* unused codes).
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*/
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struct {
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u_int :2; /* 00 */
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u_int :5;
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u_int i_op2:3; /* second-level decode */
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u_int :22;
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} i_op2;
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/* UNIMP, SETHI */
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struct {
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u_int :2; /* 00 */
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u_int i_rd:5; /* destination register */
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u_int i_op2:3; /* opcode: UNIMP or SETHI */
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u_int i_imm:22; /* immediate value */
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} i_imm22;
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/* branches: Bicc, FBfcc, CBccc */
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struct {
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u_int :2; /* 00 */
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u_int i_annul:1; /* annul bit */
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u_int i_cond:4; /* condition codes */
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u_int i_op2:3; /* opcode: {Bi,FBf,CBc}cc */
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int i_disp:22; /* branch displacement */
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} i_branch;
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/* more branches: BPcc, FBPfcc */
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struct {
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u_int :2; /* 00 */
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u_int i_annul:1; /* annul bit */
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u_int i_cond:4; /* condition codes */
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u_int i_op2:3; /* opcode: {BP,FBPf}cc */
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u_int i_cc:2; /* condition code selector */
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u_int i_pred:1; /* branch prediction bit */
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int i_disp:19; /* branch displacement */
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} i_branch_p;
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/* one last branch: BPr */
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struct {
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u_int :2; /* 00 */
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u_int i_annul:1; /* annul bit */
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u_int :1; /* 0 */
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u_int i_rcond:4; /* register condition */
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u_int :3; /* 011 */
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int i_disphi:2; /* branch displacement, hi bits */
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u_int i_pred:1; /* branch prediction bit */
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u_int i_rs1:1; /* source register 1 */
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u_int i_displo:16; /* branch displacement, lo bits */
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} i_branch_pr;
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/*
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* Format 3 instructions (memory reference; arithmetic, logical,
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* shift, and other miscellaneous operations). The second-level
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* decode almost always makes use of an `rd' and `rs1', however
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* (see also IOP3_reg and IOP3_mem).
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*
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* Beyond that, the low 14 bits may be broken up in one of three
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* different ways, if at all:
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* 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem]
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* 1 bit of imm=1 + 13 bits of signed immediate [reg & mem]
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* 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only]
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*/
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struct {
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u_int :2; /* 10 or 11 */
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u_int i_rd:5; /* destination register */
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u_int i_op3:6; /* second-level decode */
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u_int i_rs1:5; /* source register 1 */
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u_int i_low14:14; /* varies */
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} i_op3;
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/*
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* Memory forms. These set i_op=3 and use simm13 or asi layout.
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* Memory references without an ASI should use 0, but the actual
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* ASI field is simply ignored.
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*/
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struct {
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u_int :2; /* 11 only */
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u_int i_rd:5; /* destination register */
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u_int i_op3:6; /* second-level decode (see IOP3_mem) */
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u_int i_i:1; /* immediate vs asi */
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u_int i_low13:13; /* depend on i bit */
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} i_loadstore;
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/*
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* Memory and register forms.
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* These come in quite a variety and we do not
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* attempt to break them down much.
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*/
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struct {
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u_int :2; /* 10 or 11 */
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u_int i_rd:5; /* destination register */
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u_int i_op3:6; /* second-level decode */
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u_int i_rs1:5; /* source register 1 */
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u_int i_i:1; /* immediate bit (1) */
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int i_simm13:13; /* signed immediate */
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} i_simm13;
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struct {
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u_int :2; /* 10 or 11 */
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u_int i_rd:5; /* destination register */
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u_int i_op3:6; /* second-level decode */
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u_int i_rs1:5; /* source register 1 */
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u_int i_i:1; /* immediate vs asi */
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u_int i_asi:8; /* asi */
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u_int i_rs2:5; /* source register 2 */
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} i_asi;
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struct {
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u_int :2; /* 10 only (register, no memory) */
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u_int i_rd:5; /* destination register */
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u_int i_op3:6; /* second-level decode (see IOP3_reg) */
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u_int i_rs1:5; /* source register 1 */
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u_int i_opf:9; /* coprocessor 3rd-level decode */
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u_int i_rs2:5; /* source register 2 */
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} i_opf;
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/*
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* Format 4 instructions (movcc, fmovr, fmovcc, and tcc). The
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* second-level decode almost always makes use of an `rd' and either
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* `rs1' or `cond'.
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*
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* Beyond that, the low 14 bits may be broken up in one of three
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* different ways, if at all:
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* 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem]
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* 1 bit of imm=1 + 13 bits of signed immediate [reg & mem]
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* 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] */
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struct {
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u_int :2; /* 10 */
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u_int i_rd:5; /* destination register */
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u_int i_op3:6; /* second-level decode */
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u_int i_rs1:5; /* source register 1 */
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u_int i_low14:14; /* varies */
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} i_op4;
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/*
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* Move fp register on condition codes.
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*/
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struct {
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u_int :2; /* 10 */
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u_int i_rd:5; /* destination register */
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u_int i_op3:6; /* second-level decode */
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u_int :1;
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u_int i_cond:4; /* condition */
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u_int i_opf_cc:3; /* condition code register */
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u_int i_opf_low:6; /* third level decode */
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u_int i_rs2:5; /* source register */
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} i_fmovcc;
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/*
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* Move fp register on integer register.
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*/
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struct {
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u_int :2; /* 10 */
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u_int i_rd:5; /* destination register */
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u_int i_op3:6; /* second-level decode */
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u_int i_rs1:5; /* source register 1 */
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u_int :1;
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u_int i_rcond:3; /* register condition */
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u_int i_opf_low:6;
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u_int i_rs2:5; /* source register 2 */
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} i_fmovr;
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};
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/*
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* Internal macros for building instructions. These correspond 1-to-1 to
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* the names above. Note that x << y | z == (x << y) | z.
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*/
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#define _I_ANY(op, b) ((op) << 30 | (b))
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#define _I_OP2(high, op2, low) \
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_I_ANY(IOP_OP2, (high) << 25 | (op2) << 22 | (low))
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#define _I_IMM22(rd, op2, imm) \
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_I_ANY(IOP_OP2, (rd) << 25 | (op2) << 22 | (imm))
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#define _I_BRANCH(a, c, op2, disp) \
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_I_ANY(IOP_OP2, (a) << 29 | (c) << 25 | (op2) << 22 | (disp))
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#define _I_FBFCC(a, cond, disp) \
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_I_BRANCH(a, cond, IOP2_FBfcc, disp)
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#define _I_CBCCC(a, cond, disp) \
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_I_BRANCH(a, cond, IOP2_CBccc, disp)
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#define _I_SIMM(simm) (1 << 13 | ((simm) & 0x1fff))
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#define _I_OP3_GEN(form, rd, op3, rs1, low14) \
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_I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14))
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#define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \
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_I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2))
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#define _I_OP3_LS_RI(rd, op3, rs1, simm13) \
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_I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13))
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#define _I_OP3_LS_RR(rd, op3, rs1, rs2) \
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_I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2)
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#define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \
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_I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2))
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#define _I_OP3_R_RI(rd, op3, rs1, simm13) \
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_I_OP3_GEN(IOP_reg, rd, op3, rs1, _I_SIMM(simm13))
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#define _I_OP3_R_RR(rd, op3, rs1, rs2) \
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_I_OP3_GEN(IOP_reg, rd, op3, rs1, rs2)
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#define I_CALL(d) _I_ANY(IOP_CALL, d)
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#define I_UNIMP(v) _I_IMM22(0, IOP2_UNIMP, v)
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#define I_BN(a, d) _I_BRANCH(a, Icc_N, IOP2_Bicc, d)
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#define I_BE(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d)
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#define I_BZ(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d)
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#define I_BLE(a, d) _I_BRANCH(a, Icc_LE, IOP2_Bicc, d)
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#define I_BL(a, d) _I_BRANCH(a, Icc_L, IOP2_Bicc, d)
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#define I_BLEU(a, d) _I_BRANCH(a, Icc_LEU, IOP2_Bicc, d)
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#define I_BCS(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d)
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#define I_BLU(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d)
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#define I_BNEG(a, d) _I_BRANCH(a, Icc_NEG, IOP2_Bicc, d)
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#define I_BVS(a, d) _I_BRANCH(a, Icc_VS, IOP2_Bicc, d)
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#define I_BA(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d)
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#define I_B(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d)
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#define I_BNE(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d)
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#define I_BNZ(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d)
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#define I_BG(a, d) _I_BRANCH(a, Icc_G, IOP2_Bicc, d)
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#define I_BGE(a, d) _I_BRANCH(a, Icc_GE, IOP2_Bicc, d)
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#define I_BGU(a, d) _I_BRANCH(a, Icc_GU, IOP2_Bicc, d)
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#define I_BCC(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d)
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#define I_BGEU(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d)
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#define I_BPOS(a, d) _I_BRANCH(a, Icc_POS, IOP2_Bicc, d)
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#define I_BVC(a, d) _I_BRANCH(a, Icc_VC, IOP2_Bicc, d)
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#define I_SETHI(r, v) _I_IMM22(r, 4, v)
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#define I_ORri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_OR, rs1, imm)
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#define I_ORrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_OR, rs1, rs2)
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#define I_MOVi(rd, imm) _I_OP3_R_RI(rd, IOP3_OR, I_G0, imm)
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#define I_MOVr(rd, rs) _I_OP3_R_RR(rd, IOP3_OR, I_G0, rs)
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#define I_RDPSR(rd) _I_OP3_R_RR(rd, IOP3_RDPSR, 0, 0)
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#define I_JMPLri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_JMPL, rs1, imm)
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#define I_JMPLrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_JMPL, rs1, rs2)
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/*
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* (Since these are sparse, we skip the enumerations for now.)
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* FPop values. All appear in both FPop1 and FPop2 spaces, but arithmetic
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* ops should happen only with FPop1 and comparison only with FPop2.
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* The type sits in the low two bits; those bits are given as zero here.
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*/
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#define FMOV 0x00
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#define FNEG 0x04
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#define FABS 0x08
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#define FSQRT 0x28
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#define FADD 0x40
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#define FSUB 0x44
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#define FMUL 0x48
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#define FDIV 0x4c
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#define FCMP 0x50
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#define FCMPE 0x54
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#define FSMULD 0x68
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#define FDMULX 0x6c
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#define FTOX 0x80
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#define FXTOS 0x84
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#define FXTOD 0x88
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#define FXTOQ 0x8c
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#define FTOS 0xc4
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#define FTOD 0xc8
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#define FTOQ 0xcc
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#define FTOI 0xd0
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/* These are in FPop2 space */
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#define FMVFC0 0x00
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#define FMVRZ 0x24
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#define FMVFC1 0x40
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#define FMVRLEZ 0x44
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#define FMVRLZ 0x64
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#define FMVFC2 0x80
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#define FMVRNZ 0xa4
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#define FMVFC3 0xc0
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#define FMVRGZ 0xc4
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#define FMVRGEZ 0xe4
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#define FMVIC 0x100
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#define FMVXC 0x180
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|
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/*
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* FPU data types.
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*/
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#define FTYPE_LNG -1 /* data = 64-bit signed long integer */
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#define FTYPE_INT 0 /* data = 32-bit signed integer */
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#define FTYPE_SNG 1 /* data = 32-bit float */
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#define FTYPE_DBL 2 /* data = 64-bit double */
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#define FTYPE_EXT 3 /* data = 128-bit extended (quad-prec) */
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