983 lines
22 KiB
C
983 lines
22 KiB
C
/* $NetBSD: zs.c,v 1.85 2002/03/11 16:27:02 pk Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Gordon W. Ross.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Zilog Z8530 Dual UART driver (machine-dependent part)
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*
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* Runs two serial lines per chip using slave drivers.
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* Plain tty/async lines use the zs_async slave.
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* Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
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*/
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#include "opt_ddb.h"
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#include "opt_kgdb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <sys/file.h>
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#include <sys/ioctl.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/tty.h>
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#include <sys/time.h>
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#include <sys/syslog.h>
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#include <machine/bsd_openprom.h>
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#include <machine/autoconf.h>
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#include <machine/intr.h>
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#include <machine/conf.h>
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#include <machine/eeprom.h>
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#include <machine/psl.h>
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#include <machine/z8530var.h>
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#include <dev/cons.h>
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#include <dev/ic/z8530reg.h>
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#include <sparc/sparc/vaddrs.h>
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#include <sparc/sparc/auxreg.h>
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#include <sparc/sparc/auxiotwo.h>
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#include <sparc/dev/cons.h>
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#include "kbd.h" /* NKBD */
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#include "zs.h" /* NZS */
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/* Make life easier for the initialized arrays here. */
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#if NZS < 3
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#undef NZS
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#define NZS 3
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#endif
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/*
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* Some warts needed by z8530tty.c -
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* The default parity REALLY needs to be the same as the PROM uses,
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* or you can not see messages done with printf during boot-up...
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*/
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int zs_def_cflag = (CREAD | CS8 | HUPCL);
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int zs_major = 12;
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/*
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* The Sun provides a 4.9152 MHz clock to the ZS chips.
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*/
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#define PCLK (9600 * 512) /* PCLK pin input clock rate */
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/*
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* Select software interrupt bit based on TTY ipl.
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*/
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#if PIL_TTY == 1
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# define IE_ZSSOFT IE_L1
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#elif PIL_TTY == 4
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# define IE_ZSSOFT IE_L4
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#elif PIL_TTY == 6
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# define IE_ZSSOFT IE_L6
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#else
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# error "no suitable software interrupt bit"
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#endif
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#define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2))
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/* The layout of this is hardware-dependent (padding, order). */
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struct zschan {
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volatile u_char zc_csr; /* ctrl,status, and indirect access */
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u_char zc_xxx0;
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volatile u_char zc_data; /* data */
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u_char zc_xxx1;
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};
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struct zsdevice {
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/* Yes, they are backwards. */
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struct zschan zs_chan_b;
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struct zschan zs_chan_a;
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};
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/* ZS channel used as the console device (if any) */
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void *zs_conschan_get, *zs_conschan_put;
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static u_char zs_init_reg[16] = {
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0, /* 0: CMD (reset, etc.) */
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0, /* 1: No interrupts yet. */
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0, /* 2: IVECT */
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ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
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ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
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ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
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0, /* 6: TXSYNC/SYNCLO */
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0, /* 7: RXSYNC/SYNCHI */
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0, /* 8: alias for data port */
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ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR,
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0, /*10: Misc. TX/RX control bits */
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ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
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((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
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0, /*13: BAUDHI (default=9600) */
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ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
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ZSWR15_BREAK_IE,
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};
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/* Console ops */
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static int zscngetc __P((dev_t));
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static void zscnputc __P((dev_t, int));
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static void zscnpollc __P((dev_t, int));
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struct consdev zs_consdev = {
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NULL,
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NULL,
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zscngetc,
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zscnputc,
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zscnpollc,
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NULL,
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};
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/****************************************************************
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* Autoconfig
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****************************************************************/
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/* Definition of the driver for autoconfig. */
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static int zs_match_mainbus __P((struct device *, struct cfdata *, void *));
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static int zs_match_obio __P((struct device *, struct cfdata *, void *));
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static void zs_attach_mainbus __P((struct device *, struct device *, void *));
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static void zs_attach_obio __P((struct device *, struct device *, void *));
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static void zs_attach __P((struct zsc_softc *, struct zsdevice *, int));
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static int zs_print __P((void *, const char *name));
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struct cfattach zs_mainbus_ca = {
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sizeof(struct zsc_softc), zs_match_mainbus, zs_attach_mainbus
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};
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struct cfattach zs_obio_ca = {
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sizeof(struct zsc_softc), zs_match_obio, zs_attach_obio
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};
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extern struct cfdriver zs_cd;
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/* Interrupt handlers. */
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static int zshard __P((void *));
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static int zssoft __P((void *));
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static int zs_get_speed __P((struct zs_chanstate *));
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/* Console device support */
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static int zs_console_flags __P((int, int, int));
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/* Power management hooks */
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int zs_enable __P((struct zs_chanstate *));
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void zs_disable __P((struct zs_chanstate *));
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/*
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* Is the zs chip present?
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*/
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static int
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zs_match_mainbus(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct mainbus_attach_args *ma = aux;
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if (strcmp(cf->cf_driver->cd_name, ma->ma_name) != 0)
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return (0);
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return (1);
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}
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static int
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zs_match_obio(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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union obio_attach_args *uoba = aux;
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struct obio4_attach_args *oba;
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if (uoba->uoba_isobio4 == 0) {
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struct sbus_attach_args *sa = &uoba->uoba_sbus;
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if (strcmp(cf->cf_driver->cd_name, sa->sa_name) != 0)
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return (0);
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return (1);
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}
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oba = &uoba->uoba_oba4;
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return (bus_space_probe(oba->oba_bustag, oba->oba_paddr,
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1, 0, 0, NULL, NULL));
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}
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static void
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zs_attach_mainbus(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct zsc_softc *zsc = (void *) self;
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struct mainbus_attach_args *ma = aux;
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zsc->zsc_bustag = ma->ma_bustag;
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zsc->zsc_dmatag = ma->ma_dmatag;
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zsc->zsc_promunit = PROM_getpropint(ma->ma_node, "slave", -2);
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zsc->zsc_node = ma->ma_node;
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/*
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* For machines with zs on mainbus (all sun4c models), we expect
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* the device registers to be mapped by the PROM.
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*/
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zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri);
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}
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static void
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zs_attach_obio(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct zsc_softc *zsc = (void *) self;
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union obio_attach_args *uoba = aux;
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if (uoba->uoba_isobio4 == 0) {
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struct sbus_attach_args *sa = &uoba->uoba_sbus;
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void *va;
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struct zs_chanstate *cs;
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int channel;
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if (sa->sa_nintr == 0) {
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printf(" no interrupt lines\n");
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return;
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}
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/*
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* Some sun4m models (Javastations) may not map the zs device.
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*/
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if (sa->sa_npromvaddrs > 0)
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va = (void *)sa->sa_promvaddr;
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else {
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bus_space_handle_t bh;
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if (sbus_bus_map(sa->sa_bustag,
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sa->sa_slot,
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sa->sa_offset,
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sa->sa_size,
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BUS_SPACE_MAP_LINEAR, &bh) != 0) {
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printf(" cannot map zs registers\n");
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return;
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}
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va = (void *)bh;
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}
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/*
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* Check if power state can be set, e.g. Tadpole 3GX
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*/
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if (PROM_getpropint(sa->sa_node, "pwr-on-auxio2", 0))
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{
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printf (" powered via auxio2");
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for (channel = 0; channel < 2; channel++) {
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cs = &zsc->zsc_cs_store[channel];
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cs->enable = zs_enable;
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cs->disable = zs_disable;
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}
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}
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zsc->zsc_bustag = sa->sa_bustag;
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zsc->zsc_dmatag = sa->sa_dmatag;
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zsc->zsc_promunit = PROM_getpropint(sa->sa_node, "slave", -2);
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zsc->zsc_node = sa->sa_node;
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zs_attach(zsc, va, sa->sa_pri);
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} else {
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struct obio4_attach_args *oba = &uoba->uoba_oba4;
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bus_space_handle_t bh;
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bus_addr_t paddr = oba->oba_paddr;
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/*
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* As for zs on mainbus, we require a PROM mapping.
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*/
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if (bus_space_map(oba->oba_bustag,
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paddr,
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sizeof(struct zsdevice),
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BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM,
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&bh) != 0) {
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printf(" cannot map zs registers\n");
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return;
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}
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zsc->zsc_bustag = oba->oba_bustag;
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zsc->zsc_dmatag = oba->oba_dmatag;
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/* Find prom unit by physical address */
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if (cpuinfo.cpu_type == CPUTYP_4_100)
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/*
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* On the sun4/100, the top-most 4 bits are zero
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* on obio addresses; force them to 1's for the
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* sake of the comparison here.
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*/
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paddr |= 0xf0000000;
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zsc->zsc_promunit =
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(paddr == 0xf1000000) ? 0 :
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(paddr == 0xf0000000) ? 1 :
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(paddr == 0xe0000000) ? 2 : -2;
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zs_attach(zsc, (void *)bh, oba->oba_pri);
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}
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}
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/*
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* Attach a found zs.
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*
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* USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR
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* SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE?
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*/
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static void
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zs_attach(zsc, zsd, pri)
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struct zsc_softc *zsc;
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struct zsdevice *zsd;
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int pri;
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{
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struct zsc_attach_args zsc_args;
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struct zs_chanstate *cs;
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int s, channel;
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static int didintr, prevpri;
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if (zsd == NULL) {
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printf("configuration incomplete\n");
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return;
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}
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printf(" softpri %d\n", PIL_TTY);
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/*
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* Initialize software state for each channel.
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*/
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for (channel = 0; channel < 2; channel++) {
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struct zschan *zc;
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zsc_args.channel = channel;
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cs = &zsc->zsc_cs_store[channel];
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zsc->zsc_cs[channel] = cs;
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cs->cs_channel = channel;
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cs->cs_private = NULL;
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cs->cs_ops = &zsops_null;
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cs->cs_brg_clk = PCLK / 16;
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zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b;
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zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit,
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zsc->zsc_node,
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channel);
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if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) {
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zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV;
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zsc_args.consdev = &zs_consdev;
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}
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if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) {
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zs_conschan_get = zc;
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}
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if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) {
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zs_conschan_put = zc;
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}
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/* Childs need to set cn_dev, etc */
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cs->cs_reg_csr = &zc->zc_csr;
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cs->cs_reg_data = &zc->zc_data;
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bcopy(zs_init_reg, cs->cs_creg, 16);
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bcopy(zs_init_reg, cs->cs_preg, 16);
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/* XXX: Consult PROM properties for this?! */
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cs->cs_defspeed = zs_get_speed(cs);
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cs->cs_defcflag = zs_def_cflag;
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/* Make these correspond to cs_defcflag (-crtscts) */
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cs->cs_rr0_dcd = ZSRR0_DCD;
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cs->cs_rr0_cts = 0;
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cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
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cs->cs_wr5_rts = 0;
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/*
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* Clear the master interrupt enable.
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* The INTENA is common to both channels,
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* so just do it on the A channel.
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*/
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if (channel == 0) {
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zs_write_reg(cs, 9, 0);
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}
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/*
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* Look for a child driver for this channel.
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* The child attach will setup the hardware.
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*/
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if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print)) {
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/* No sub-driver. Just reset it. */
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u_char reset = (channel == 0) ?
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ZSWR9_A_RESET : ZSWR9_B_RESET;
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s = splzs();
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zs_write_reg(cs, 9, reset);
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splx(s);
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}
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}
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/*
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* Now safe to install interrupt handlers. Note the arguments
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* to the interrupt handlers aren't used. Note, we only do this
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* once since both SCCs interrupt at the same level and vector.
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*/
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if (!didintr) {
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didintr = 1;
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prevpri = pri;
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bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0,
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zshard, NULL);
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bus_intr_establish(zsc->zsc_bustag, PIL_TTY,
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IPL_SOFTSERIAL,
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BUS_INTR_ESTABLISH_SOFTINTR,
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zssoft, NULL);
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} else if (pri != prevpri)
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panic("broken zs interrupt scheme");
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evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL,
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zsc->zsc_dev.dv_xname, "intr");
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/*
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* Set the master interrupt enable and interrupt vector.
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* (common to both channels, do it on A)
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*/
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cs = zsc->zsc_cs[0];
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s = splhigh();
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/* interrupt vector */
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zs_write_reg(cs, 2, zs_init_reg[2]);
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/* master interrupt control (enable) */
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zs_write_reg(cs, 9, zs_init_reg[9]);
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splx(s);
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#if 0
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/*
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* XXX: L1A hack - We would like to be able to break into
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* the debugger during the rest of autoconfiguration, so
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* lower interrupts just enough to let zs interrupts in.
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* This is done after both zs devices are attached.
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*/
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if (zsc->zsc_promunit == 1) {
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printf("zs1: enabling zs interrupts\n");
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(void)splfd(); /* XXX: splzs - 1 */
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}
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#endif
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|
}
|
|
|
|
static int
|
|
zs_print(aux, name)
|
|
void *aux;
|
|
const char *name;
|
|
{
|
|
struct zsc_attach_args *args = aux;
|
|
|
|
if (name != NULL)
|
|
printf("%s: ", name);
|
|
|
|
if (args->channel != -1)
|
|
printf(" channel %d", args->channel);
|
|
|
|
return (UNCONF);
|
|
}
|
|
|
|
static volatile int zssoftpending;
|
|
|
|
/*
|
|
* Our ZS chips all share a common, autovectored interrupt,
|
|
* so we have to look at all of them on each interrupt.
|
|
*/
|
|
static int
|
|
zshard(arg)
|
|
void *arg;
|
|
{
|
|
struct zsc_softc *zsc;
|
|
int unit, rr3, rval, softreq;
|
|
|
|
rval = softreq = 0;
|
|
for (unit = 0; unit < zs_cd.cd_ndevs; unit++) {
|
|
struct zs_chanstate *cs;
|
|
|
|
zsc = zs_cd.cd_devs[unit];
|
|
if (zsc == NULL)
|
|
continue;
|
|
rr3 = zsc_intr_hard(zsc);
|
|
/* Count up the interrupts. */
|
|
if (rr3) {
|
|
rval |= rr3;
|
|
zsc->zsc_intrcnt.ev_count++;
|
|
}
|
|
if ((cs = zsc->zsc_cs[0]) != NULL)
|
|
softreq |= cs->cs_softreq;
|
|
if ((cs = zsc->zsc_cs[1]) != NULL)
|
|
softreq |= cs->cs_softreq;
|
|
}
|
|
|
|
/* We are at splzs here, so no need to lock. */
|
|
if (softreq && (zssoftpending == 0)) {
|
|
zssoftpending = IE_ZSSOFT;
|
|
#if defined(SUN4M)
|
|
if (CPU_ISSUN4M)
|
|
raise(0, PIL_TTY);
|
|
else
|
|
#endif
|
|
ienab_bis(IE_ZSSOFT);
|
|
}
|
|
return (rval);
|
|
}
|
|
|
|
/*
|
|
* Similar scheme as for zshard (look at all of them)
|
|
*/
|
|
static int
|
|
zssoft(arg)
|
|
void *arg;
|
|
{
|
|
struct zsc_softc *zsc;
|
|
int s, unit;
|
|
|
|
/* This is not the only ISR on this IPL. */
|
|
if (zssoftpending == 0)
|
|
return (0);
|
|
|
|
/*
|
|
* The soft intr. bit will be set by zshard only if
|
|
* the variable zssoftpending is zero. The order of
|
|
* these next two statements prevents our clearing
|
|
* the soft intr bit just after zshard has set it.
|
|
*/
|
|
/* ienab_bic(IE_ZSSOFT); */
|
|
zssoftpending = 0;
|
|
|
|
/* Make sure we call the tty layer at spltty. */
|
|
s = spltty();
|
|
for (unit = 0; unit < zs_cd.cd_ndevs; unit++) {
|
|
zsc = zs_cd.cd_devs[unit];
|
|
if (zsc == NULL)
|
|
continue;
|
|
(void)zsc_intr_soft(zsc);
|
|
}
|
|
splx(s);
|
|
return (1);
|
|
}
|
|
|
|
|
|
/*
|
|
* Compute the current baud rate given a ZS channel.
|
|
*/
|
|
static int
|
|
zs_get_speed(cs)
|
|
struct zs_chanstate *cs;
|
|
{
|
|
int tconst;
|
|
|
|
tconst = zs_read_reg(cs, 12);
|
|
tconst |= zs_read_reg(cs, 13) << 8;
|
|
return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
|
|
}
|
|
|
|
/*
|
|
* MD functions for setting the baud rate and control modes.
|
|
*/
|
|
int
|
|
zs_set_speed(cs, bps)
|
|
struct zs_chanstate *cs;
|
|
int bps; /* bits per second */
|
|
{
|
|
int tconst, real_bps;
|
|
|
|
if (bps == 0)
|
|
return (0);
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (cs->cs_brg_clk == 0)
|
|
panic("zs_set_speed");
|
|
#endif
|
|
|
|
tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
|
|
if (tconst < 0)
|
|
return (EINVAL);
|
|
|
|
/* Convert back to make sure we can do it. */
|
|
real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
|
|
|
|
/* XXX - Allow some tolerance here? */
|
|
if (real_bps != bps)
|
|
return (EINVAL);
|
|
|
|
cs->cs_preg[12] = tconst;
|
|
cs->cs_preg[13] = tconst >> 8;
|
|
|
|
/* Caller will stuff the pending registers. */
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
zs_set_modes(cs, cflag)
|
|
struct zs_chanstate *cs;
|
|
int cflag; /* bits per second */
|
|
{
|
|
int s;
|
|
|
|
/*
|
|
* Output hardware flow control on the chip is horrendous:
|
|
* if carrier detect drops, the receiver is disabled, and if
|
|
* CTS drops, the transmitter is stoped IN MID CHARACTER!
|
|
* Therefore, NEVER set the HFC bit, and instead use the
|
|
* status interrupt to detect CTS changes.
|
|
*/
|
|
s = splzs();
|
|
cs->cs_rr0_pps = 0;
|
|
if ((cflag & (CLOCAL | MDMBUF)) != 0) {
|
|
cs->cs_rr0_dcd = 0;
|
|
if ((cflag & MDMBUF) == 0)
|
|
cs->cs_rr0_pps = ZSRR0_DCD;
|
|
} else
|
|
cs->cs_rr0_dcd = ZSRR0_DCD;
|
|
if ((cflag & CRTSCTS) != 0) {
|
|
cs->cs_wr5_dtr = ZSWR5_DTR;
|
|
cs->cs_wr5_rts = ZSWR5_RTS;
|
|
cs->cs_rr0_cts = ZSRR0_CTS;
|
|
} else if ((cflag & CDTRCTS) != 0) {
|
|
cs->cs_wr5_dtr = 0;
|
|
cs->cs_wr5_rts = ZSWR5_DTR;
|
|
cs->cs_rr0_cts = ZSRR0_CTS;
|
|
} else if ((cflag & MDMBUF) != 0) {
|
|
cs->cs_wr5_dtr = 0;
|
|
cs->cs_wr5_rts = ZSWR5_DTR;
|
|
cs->cs_rr0_cts = ZSRR0_DCD;
|
|
} else {
|
|
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
|
|
cs->cs_wr5_rts = 0;
|
|
cs->cs_rr0_cts = 0;
|
|
}
|
|
splx(s);
|
|
|
|
/* Caller will stuff the pending registers. */
|
|
return (0);
|
|
}
|
|
|
|
|
|
/*
|
|
* Read or write the chip with suitable delays.
|
|
*/
|
|
|
|
u_char
|
|
zs_read_reg(cs, reg)
|
|
struct zs_chanstate *cs;
|
|
u_char reg;
|
|
{
|
|
u_char val;
|
|
|
|
*cs->cs_reg_csr = reg;
|
|
ZS_DELAY();
|
|
val = *cs->cs_reg_csr;
|
|
ZS_DELAY();
|
|
return (val);
|
|
}
|
|
|
|
void
|
|
zs_write_reg(cs, reg, val)
|
|
struct zs_chanstate *cs;
|
|
u_char reg, val;
|
|
{
|
|
*cs->cs_reg_csr = reg;
|
|
ZS_DELAY();
|
|
*cs->cs_reg_csr = val;
|
|
ZS_DELAY();
|
|
}
|
|
|
|
u_char
|
|
zs_read_csr(cs)
|
|
struct zs_chanstate *cs;
|
|
{
|
|
u_char val;
|
|
|
|
val = *cs->cs_reg_csr;
|
|
ZS_DELAY();
|
|
return (val);
|
|
}
|
|
|
|
void
|
|
zs_write_csr(cs, val)
|
|
struct zs_chanstate *cs;
|
|
u_char val;
|
|
{
|
|
*cs->cs_reg_csr = val;
|
|
ZS_DELAY();
|
|
}
|
|
|
|
u_char
|
|
zs_read_data(cs)
|
|
struct zs_chanstate *cs;
|
|
{
|
|
u_char val;
|
|
|
|
val = *cs->cs_reg_data;
|
|
ZS_DELAY();
|
|
return (val);
|
|
}
|
|
|
|
void zs_write_data(cs, val)
|
|
struct zs_chanstate *cs;
|
|
u_char val;
|
|
{
|
|
*cs->cs_reg_data = val;
|
|
ZS_DELAY();
|
|
}
|
|
|
|
/****************************************************************
|
|
* Console support functions (Sun specific!)
|
|
* Note: this code is allowed to know about the layout of
|
|
* the chip registers, and uses that to keep things simple.
|
|
* XXX - I think I like the mvme167 code better. -gwr
|
|
****************************************************************/
|
|
|
|
/*
|
|
* Handle user request to enter kernel debugger.
|
|
*/
|
|
void
|
|
zs_abort(cs)
|
|
struct zs_chanstate *cs;
|
|
{
|
|
struct zschan *zc = zs_conschan_get;
|
|
int rr0;
|
|
|
|
/* Wait for end of break to avoid PROM abort. */
|
|
/* XXX - Limit the wait? */
|
|
do {
|
|
rr0 = zc->zc_csr;
|
|
ZS_DELAY();
|
|
} while (rr0 & ZSRR0_BREAK);
|
|
|
|
#if defined(KGDB)
|
|
zskgdb(cs);
|
|
#elif defined(DDB)
|
|
Debugger();
|
|
#else
|
|
printf("stopping on keyboard abort\n");
|
|
callrom();
|
|
#endif
|
|
}
|
|
|
|
int zs_getc __P((void *arg));
|
|
void zs_putc __P((void *arg, int c));
|
|
|
|
/*
|
|
* Polled input char.
|
|
*/
|
|
int
|
|
zs_getc(arg)
|
|
void *arg;
|
|
{
|
|
struct zschan *zc = arg;
|
|
int s, c, rr0;
|
|
|
|
s = splhigh();
|
|
/* Wait for a character to arrive. */
|
|
do {
|
|
rr0 = zc->zc_csr;
|
|
ZS_DELAY();
|
|
} while ((rr0 & ZSRR0_RX_READY) == 0);
|
|
|
|
c = zc->zc_data;
|
|
ZS_DELAY();
|
|
splx(s);
|
|
|
|
/*
|
|
* This is used by the kd driver to read scan codes,
|
|
* so don't translate '\r' ==> '\n' here...
|
|
*/
|
|
return (c);
|
|
}
|
|
|
|
/*
|
|
* Polled output char.
|
|
*/
|
|
void
|
|
zs_putc(arg, c)
|
|
void *arg;
|
|
int c;
|
|
{
|
|
struct zschan *zc = arg;
|
|
int s, rr0;
|
|
|
|
s = splhigh();
|
|
|
|
/* Wait for transmitter to become ready. */
|
|
do {
|
|
rr0 = zc->zc_csr;
|
|
ZS_DELAY();
|
|
} while ((rr0 & ZSRR0_TX_READY) == 0);
|
|
|
|
/*
|
|
* Send the next character.
|
|
* Now you'd think that this could be followed by a ZS_DELAY()
|
|
* just like all the other chip accesses, but it turns out that
|
|
* the `transmit-ready' interrupt isn't de-asserted until
|
|
* some period of time after the register write completes
|
|
* (more than a couple instructions). So to avoid stray
|
|
* interrupts we put in the 2us delay regardless of cpu model.
|
|
*/
|
|
zc->zc_data = c;
|
|
delay(2);
|
|
|
|
splx(s);
|
|
}
|
|
|
|
/*****************************************************************/
|
|
/*
|
|
* Polled console input putchar.
|
|
*/
|
|
int
|
|
zscngetc(dev)
|
|
dev_t dev;
|
|
{
|
|
return (zs_getc(zs_conschan_get));
|
|
}
|
|
|
|
/*
|
|
* Polled console output putchar.
|
|
*/
|
|
void
|
|
zscnputc(dev, c)
|
|
dev_t dev;
|
|
int c;
|
|
{
|
|
zs_putc(zs_conschan_put, c);
|
|
}
|
|
|
|
void
|
|
zscnpollc(dev, on)
|
|
dev_t dev;
|
|
int on;
|
|
{
|
|
/* No action needed */
|
|
}
|
|
|
|
int
|
|
zs_console_flags(promunit, node, channel)
|
|
int promunit;
|
|
int node;
|
|
int channel;
|
|
{
|
|
int cookie, flags = 0;
|
|
|
|
switch (prom_version()) {
|
|
case PROM_OLDMON:
|
|
case PROM_OBP_V0:
|
|
/*
|
|
* Use `promunit' and `channel' to derive the PROM
|
|
* stdio handles that correspond to this device.
|
|
*/
|
|
if (promunit == 0)
|
|
cookie = PROMDEV_TTYA + channel;
|
|
else if (promunit == 1 && channel == 0)
|
|
cookie = PROMDEV_KBD;
|
|
else
|
|
cookie = -1;
|
|
|
|
if (cookie == prom_stdin())
|
|
flags |= ZS_HWFLAG_CONSOLE_INPUT;
|
|
|
|
/*
|
|
* Prevent the keyboard from matching the output device
|
|
* (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!).
|
|
*/
|
|
if (cookie != PROMDEV_KBD && cookie == prom_stdout())
|
|
flags |= ZS_HWFLAG_CONSOLE_OUTPUT;
|
|
|
|
break;
|
|
|
|
case PROM_OBP_V2:
|
|
case PROM_OBP_V3:
|
|
case PROM_OPENFIRM:
|
|
|
|
/*
|
|
* Match the nodes and device arguments prepared by
|
|
* consinit() against our device node and channel.
|
|
* (The device argument is the part of the OBP path
|
|
* following the colon, as in `/obio/zs@0,100000:a')
|
|
*/
|
|
|
|
/* Default to channel 0 if there are no explicit prom args */
|
|
cookie = 0;
|
|
|
|
if (node == prom_stdin_node) {
|
|
if (prom_stdin_args[0] != '\0')
|
|
/* Translate (a,b) -> (0,1) */
|
|
cookie = prom_stdin_args[0] - 'a';
|
|
|
|
if (channel == cookie)
|
|
flags |= ZS_HWFLAG_CONSOLE_INPUT;
|
|
}
|
|
|
|
if (node == prom_stdout_node) {
|
|
if (prom_stdout_args[0] != '\0')
|
|
/* Translate (a,b) -> (0,1) */
|
|
cookie = prom_stdout_args[0] - 'a';
|
|
|
|
if (channel == cookie)
|
|
flags |= ZS_HWFLAG_CONSOLE_OUTPUT;
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return (flags);
|
|
}
|
|
|
|
/*
|
|
* Power management hooks for zsopen() and zsclose().
|
|
* We use them to power on/off the ports, if necessary.
|
|
*/
|
|
int
|
|
zs_enable(cs)
|
|
struct zs_chanstate *cs;
|
|
{
|
|
auxiotwoserialendis (ZS_ENABLE);
|
|
cs->enabled = 1;
|
|
return(0);
|
|
}
|
|
|
|
void
|
|
zs_disable(cs)
|
|
struct zs_chanstate *cs;
|
|
{
|
|
auxiotwoserialendis (ZS_DISABLE);
|
|
cs->enabled = 0;
|
|
}
|