740 lines
18 KiB
ArmAsm
740 lines
18 KiB
ArmAsm
/* $NetBSD: trap_subr.S,v 1.5 2002/08/02 03:46:42 chs Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* NOTICE: This is not a standalone file. to use it, #include it in
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* your port's locore.S, like so:
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*
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* #include <powerpc/ibm4xx/trap_subr.S>
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*/
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/*
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* Data used during primary/secondary traps/interrupts
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*/
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#define tempsave 0x2e0 /* primary save area for trap handling */
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#define disisave 0x3e0 /* primary save area for dsi/isi traps */
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#define exitsave 0x4e0 /* use this so trap return does not conflict */
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/*
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* XXX Interrupt and spill stacks need to be per-CPU.
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*/
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.data
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.align 4
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intstk:
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.space INTSTK /* interrupt stack */
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GLOBAL(intr_depth)
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.long -1 /* in-use marker */
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.comm spillstk,SPILLSTK,8
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#if defined(MULTIPROCESSOR)
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#define GET_PCB(rX) \
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GET_CPUINFO(rX); \
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lwz rX,CI_CURPCB(rX)
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#else
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#define GET_PCB(x) \
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lis 1,_C_LABEL(curpcb)@ha; \
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lwz 1,_C_LABEL(curpcb)@l(1)
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#endif
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#define STANDARD_PROLOG(savearea) \
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mtsprg 1,1; /* save SP */ \
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stmw 28,savearea(0); /* free r28-r31 */ \
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mflr 28; /* save LR */ \
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mfcr 29; /* save CR */ \
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mfsrr1 31; /* Test whether we already had PR set */ \
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mtcr 31; \
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bc 4,17,1f; /* branch if PSL_PR is clear */ \
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GET_PCB(1); \
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addi 1,1,USPACE; /* stack is top of user struct */ \
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1:
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#define CRITICAL_PROLOG(savearea) \
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mtsprg 1,1; /* save SP */ \
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stmw 28,savearea(0); /* free r28-r31 */ \
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mflr 28; /* save LR */ \
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mfcr 29; /* save CR */ \
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mfsrr2 30; /* Fake a standard trap */ \
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mtsrr0 30; \
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mfsrr3 31; /* Test whether we already had PR set */ \
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mtsrr1 31; \
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mtcr 31; \
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bc 4,17,1f; /* branch if PSL_PR is clear */ \
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GET_PCB(1); \
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addi 1,1,USPACE; /* stack is top of user struct */ \
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1:
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/* Standard handler saves r1,r28-31,LR,CR, sets up the stack and calls s_trap */
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#define STANDARD_EXC_HANDLER(name)\
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.globl _C_LABEL(name ## trap),_C_LABEL(name ## size) ; \
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_C_LABEL(name ## trap): \
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STANDARD_PROLOG(tempsave); \
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bla s_trap ; \
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_C_LABEL(name ## size) = .-_C_LABEL(name ## trap)
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/* Access exceptions also need DEAR and ESR saved */
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#define ACCESS_EXC_HANDLER(name)\
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.globl _C_LABEL(name ## trap),_C_LABEL(name ## size) ; \
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_C_LABEL(name ## trap): \
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STANDARD_PROLOG(tempsave); \
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mfdear 30; \
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mfesr 31; \
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stmw 30,16+tempsave(0); \
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bla s_trap ; \
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_C_LABEL(name ## size) = .-_C_LABEL(name ## trap)
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/* Maybe this should call ddb.... */
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#define CRITICAL_EXC_HANDLER(name)\
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.globl _C_LABEL(name ## trap),_C_LABEL(name ## size) ; \
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_C_LABEL(name ## trap): \
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CRITICAL_PROLOG(tempsave); \
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bla s_trap ; \
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_C_LABEL(name ## size) = .-_C_LABEL(name ## trap)
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/*
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* This code gets copied to all the trap vectors
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* (except ISI/DSI, ALI, the interrupts, and possibly the debugging
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* traps when using IPKDB).
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*/
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.text
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STANDARD_EXC_HANDLER(default)
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ACCESS_EXC_HANDLER(ali)
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ACCESS_EXC_HANDLER(dsi)
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ACCESS_EXC_HANDLER(isi)
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STANDARD_EXC_HANDLER(debug)
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CRITICAL_EXC_HANDLER(mchk)
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/*
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* This one for the external interrupt handler.
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*/
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.globl _C_LABEL(extint),_C_LABEL(extsize)
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_C_LABEL(extint):
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mtsprg 1,1 /* save SP */
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stmw 28,tempsave(0) /* free r28-r31 */
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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mfxer 30 /* save XER */
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lis 1,intstk+INTSTK@ha /* get interrupt stack */
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addi 1,1,intstk+INTSTK@l
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lwz 31,0(1) /* were we already running on intstk? */
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addic. 31,31,1
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stw 31,0(1)
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beq 1f
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mfsprg 1,1 /* yes, get old SP */
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1:
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ba extintr
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_C_LABEL(extsize) = .-_C_LABEL(extint)
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#ifdef DDB
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#define ddbsave 0xde0 /* primary save area for DDB */
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/*
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* In case of DDB we want a separate trap catcher for it
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*/
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.local ddbstk
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.comm ddbstk,INTSTK,8 /* ddb stack */
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.globl _C_LABEL(ddblow),_C_LABEL(ddbsize)
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_C_LABEL(ddblow):
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mtsprg 1,1 /* save SP */
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stmw 28,ddbsave(0) /* free r28-r31 */
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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lis 1,ddbstk+INTSTK@ha /* get new SP */
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addi 1,1,ddbstk+INTSTK@l
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bla ddbtrap
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_C_LABEL(ddbsize) = .-_C_LABEL(ddblow)
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#endif /* DDB */
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#ifdef IPKDB
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#define ipkdbsave 0xde0 /* primary save area for IPKDB */
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/*
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* In case of IPKDB we want a separate trap catcher for it
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*/
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.local ipkdbstk
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.comm ipkdbstk,INTSTK,8 /* ipkdb stack */
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.globl _C_LABEL(ipkdblow),_C_LABEL(ipkdbsize)
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_C_LABEL(ipkdblow):
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mtsprg 1,1 /* save SP */
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stmw 28,ipkdbsave(0) /* free r28-r31 */
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mflr 28 /* save LR */
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mfcr 29 /* save CR */
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lis 1,ipkdbstk+INTSTK@ha /* get new SP */
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addi 1,1,ipkdbstk+INTSTK@l
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bla ipkdbtrap
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_C_LABEL(ipkdbsize) = .-_C_LABEL(ipkdblow)
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#endif /* IPKDB */
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#ifdef DEBUG
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#define TRAP_IF_ZERO(r) tweqi r,0
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#else
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#define TRAP_IF_ZERO(r)
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#endif
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/*
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* FRAME_SETUP assumes:
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* SPRG1 SP (1)
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* savearea r28-r31,DEAR,ESR (DEAR & ESR only for DSI traps)
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* 28 LR
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* 29 CR
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* 1 kernel stack
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* LR trap type
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* SRR0/1 as at start of trap
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*/
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#define FRAME_SETUP(savearea) \
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/* Have to enable translation to allow access of kernel stack: */ \
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mfsrr0 30; \
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mfsrr1 31; \
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stmw 30,savearea+24(0); \
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mfpid 30; \
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li 31,KERNEL_PID; \
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mtpid 31; \
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mfmsr 31; \
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ori 31,31,(PSL_DR|PSL_IR)@l; \
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mtmsr 31; \
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isync; \
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mfsprg 31,1; \
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stwu 31,-FRAMELEN(1); \
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stw 30,FRAME_PID+8(1); \
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stw 0,FRAME_0+8(1); \
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stw 31,FRAME_1+8(1); \
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stw 28,FRAME_LR+8(1); \
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stw 29,FRAME_CR+8(1); \
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lmw 28,savearea(0); \
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stmw 2,FRAME_2+8(1); \
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lmw 28,savearea+16(0); \
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mfxer 3; \
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mfctr 4; \
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mflr 5; \
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andi. 5,5,0xff00; \
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stw 3,FRAME_XER+8(1); \
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stw 4,FRAME_CTR+8(1); \
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stw 5,FRAME_EXC+8(1); \
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stw 28,FRAME_DEAR+8(1); \
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stw 29,FRAME_ESR+8(1); \
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stw 30,FRAME_SRR0+8(1); \
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stw 31,FRAME_SRR1+8(1)
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#define FRAME_LEAVE(savearea) \
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/* Now restore regs: */ \
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lwz 3,FRAME_PID+8(1); \
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lwz 4,FRAME_SRR1+8(1); \
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bl _C_LABEL(ctx_setup); \
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TRAP_IF_ZERO(r3); \
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stw 3,FRAME_PID+8(1); \
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lmw 26,FRAME_LR+8(1); \
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mtlr 26; \
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mtcr 27; \
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mtxer 28; \
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mtctr 29; \
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mtsrr0 30; \
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mtsrr1 31; \
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lmw 2,FRAME_2+8(1); \
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lwz 0,FRAME_0+8(1); \
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stmw 29,savearea(0); \
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lwz 30,FRAME_PID+8(1); \
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lwz 1,FRAME_1+8(1); \
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mfmsr 31; \
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li 29,(PSL_DR|PSL_IR)@l; \
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andc 31,31,29; \
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mfcr 29; \
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mtcr 29; \
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mtmsr 31; \
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isync; \
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TRAP_IF_ZERO(r30); \
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mtpid 30; \
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lmw 29,savearea(0)
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realtrap: /* entry point after IPKDB is done with exception */
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/* Test whether we already had PR set */
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mfsrr1 1
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mtcr 1
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mfsprg 1,1 /* restore SP (might have been
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overwritten) */
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bc 4,17,s_trap /* branch if PSL_PR is false */
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lis 1,_C_LABEL(curpcb)@ha
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lwz 1,_C_LABEL(curpcb)@l(1)
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addi 1,1,USPACE /* stack is top of user struct */
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/*
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* Now the common trap catching code.
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*/
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s_trap:
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FRAME_SETUP(tempsave)
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/* Now we can recover interrupts again: */
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trapagain:
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wrteei 1 /* Enable interrupts */
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/* Call C trap code: */
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addi 3,1,8
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bl _C_LABEL(trap)
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.globl _C_LABEL(trapexit)
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_C_LABEL(trapexit):
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/* Disable interrupts: */
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wrteei 0
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/* Test AST pending: */
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lwz 5,FRAME_SRR1+8(1)
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mtcr 5
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bc 4,17,1f /* branch if PSL_PR is false */
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#if defined(MULTIPROCESSOR)
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GET_CPUINFO(3)
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lwz 4,CI_ASTPENDING(3)
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#else
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lis 3,_C_LABEL(astpending)@ha
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lwz 4,_C_LABEL(astpending)@l(3)
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#endif
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andi. 4,4,1
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beq 1f
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li 6,EXC_AST
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stw 6,FRAME_EXC+8(1)
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b trapagain
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1:
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FRAME_LEAVE(exitsave)
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rfi
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ba . /* Protect against prefetch */
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.globl _C_LABEL(sctrap),_C_LABEL(scsize)
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_C_LABEL(sctrap):
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STANDARD_PROLOG(tempsave);
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bla s_sctrap
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_C_LABEL(scsize) = .-_C_LABEL(sctrap)
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s_sctrap:
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FRAME_SETUP(tempsave)
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/* Now we can recover interrupts again: */
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wrteei 1 /* Enable interrupts */
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/* Call the appropriate syscall handler: */
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addi 3,1,8
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lis 4,_C_LABEL(curproc)@ha
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lwz 4,_C_LABEL(curproc)@l(4)
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lwz 4,P_MD_SYSCALL@l(4)
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mtctr 4
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bctrl
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/* Disable interrupts: */
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wrteei 0
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/* Test AST pending: */
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lwz 5,FRAME_SRR1+8(1)
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mtcr 5
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bc 4,17,1f /* branch if PSL_PR is false */
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#if defined(MULTIPROCESSOR)
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GET_CPUINFO(3)
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lwz 4,CI_ASTPENDING(3)
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#else
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lis 3,_C_LABEL(astpending)@ha
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lwz 4,_C_LABEL(astpending)@l(3)
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#endif
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andi. 4,4,1
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beq 1f
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li 6,EXC_AST
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stw 6,FRAME_EXC+8(1)
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b trapagain
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1:
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FRAME_LEAVE(exitsave)
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rfi
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ba . /* Protect against prefetch */
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/*
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* External interrupt second level handler
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*/
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#define INTRENTER \
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/* Save non-volatile registers: */ \
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stwu 1,-92(1); /* temporarily */ \
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stw 0,84(1); \
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mfsprg 0,1; /* get original SP */ \
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stw 0,0(1); /* and store it */ \
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stw 3,80(1); \
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stw 4,76(1); \
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stw 5,72(1); \
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stw 6,68(1); \
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stw 7,64(1); \
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stw 8,60(1); \
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stw 9,56(1); \
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stw 10,52(1); \
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stw 11,48(1); \
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stw 12,44(1); \
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stw 28,40(1); /* saved LR */ \
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stw 29,36(1); /* saved CR */ \
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stw 30,32(1); /* saved XER */ \
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lmw 28,tempsave(0); /* restore r28-r31 */ \
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mfctr 6; \
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lis 5,_C_LABEL(intr_depth)@ha; \
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lwz 5,_C_LABEL(intr_depth)@l(5); \
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mfsrr0 4; \
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mfsrr1 3; \
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stw 6,28(1); \
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stw 5,20(1); \
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stw 4,12(1); \
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stw 3,8(1); \
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mfpid 0; /* get currect PID register */ \
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stw 0,88(1) ; \
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li 0, KERNEL_PID; \
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mtpid 0; \
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/* interrupts are recoverable here, and enable translation */ \
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mfmsr 5; \
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ori 5,5,(PSL_IR|PSL_DR); \
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mtmsr 5; \
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isync
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.globl _C_LABEL(extint_call)
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extintr:
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INTRENTER
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_C_LABEL(extint_call):
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bl _C_LABEL(extint_call) /* to be filled in later */
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intr_exit:
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/* Disable interrupts (should already be disabled) and MMU here: */
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wrteei 0
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isync
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lwz 3,88(1)
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lwz 4,8(1) /* Load srr1 */
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bl _C_LABEL(ctx_setup) /* Get proper ctx */
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mfmsr 5
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lis 4,(PSL_EE|PSL_DR|PSL_IR)@h
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ori 4,4,(PSL_EE|PSL_DR|PSL_IR)@l
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andc 5,5,4
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mtmsr 5
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isync
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mtpid 3 /* Load CTX */
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/* restore possibly overwritten registers: */
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lwz 12,44(1)
|
|
lwz 11,48(1)
|
|
lwz 10,52(1)
|
|
lwz 9,56(1)
|
|
lwz 8,60(1)
|
|
lwz 7,64(1)
|
|
lwz 6,8(1)
|
|
lwz 5,12(1)
|
|
lwz 4,28(1)
|
|
lwz 3,32(1)
|
|
mtsrr1 6
|
|
mtsrr0 5
|
|
mtctr 4
|
|
mtxer 3
|
|
/* Returning to user mode? */
|
|
mtcr 6 /* saved SRR1 */
|
|
bc 4,17,1f /* branch if PSL_PR is false */
|
|
|
|
#if defined(MULTIPROCESSOR)
|
|
lwz 4,CI_ASTPENDING(4) /* Test AST pending */
|
|
#else
|
|
lis 3,_C_LABEL(astpending)@ha /* Test AST pending */
|
|
lwz 4,_C_LABEL(astpending)@l(3)
|
|
#endif
|
|
andi. 4,4,1
|
|
beq 1f
|
|
/* Setup for entry to realtrap: */
|
|
lwz 3,0(1) /* get saved SP */
|
|
mtsprg 1,3
|
|
li 6,EXC_AST
|
|
stmw 28,tempsave(0) /* establish tempsave again */
|
|
mtlr 6
|
|
lwz 28,40(1) /* saved LR */
|
|
lwz 29,36(1) /* saved CR */
|
|
lwz 6,68(1)
|
|
lwz 5,72(1)
|
|
lwz 4,76(1)
|
|
lwz 3,80(1)
|
|
lwz 0,84(1)
|
|
lis 30,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
|
lwz 31,_C_LABEL(intr_depth)@l(30)
|
|
addi 31,31,-1
|
|
stw 31,_C_LABEL(intr_depth)@l(30)
|
|
b realtrap
|
|
1:
|
|
/* Here is the normal exit of extintr: */
|
|
lwz 5,36(1)
|
|
lwz 6,40(1)
|
|
mtcr 5
|
|
mtlr 6
|
|
lwz 6,68(1)
|
|
lwz 5,72(1)
|
|
lis 3,_C_LABEL(intr_depth)@ha /* adjust reentrancy count */
|
|
lwz 4,_C_LABEL(intr_depth)@l(3)
|
|
addi 4,4,-1
|
|
stw 4,_C_LABEL(intr_depth)@l(3)
|
|
lwz 4,76(1)
|
|
lwz 3,80(1)
|
|
lwz 0,84(1)
|
|
lwz 1,0(1)
|
|
rfi
|
|
ba . /* Protect against prefetch */
|
|
|
|
/*
|
|
* PIT interrupt handler.
|
|
*/
|
|
.align 5
|
|
_C_LABEL(pitint):
|
|
mtsprg 1,1 /* save SP */
|
|
stmw 28,tempsave(0) /* free r28-r31 */
|
|
mflr 28 /* save LR */
|
|
mfcr 29 /* save CR */
|
|
mfxer 30 /* save XER */
|
|
lis 1,intstk+INTSTK@ha /* get interrupt stack */
|
|
addi 1,1,intstk+INTSTK@l
|
|
lwz 31,0(1) /* were we already running on intstk? */
|
|
addic. 31,31,1
|
|
stw 31,0(1)
|
|
beq 1f
|
|
mfsprg 1,1 /* yes, get old SP */
|
|
1:
|
|
INTRENTER
|
|
addi 3,1,8 /* intr frame */
|
|
bl _C_LABEL(decr_intr)
|
|
b intr_exit
|
|
|
|
/*
|
|
* FIT interrupt handler.
|
|
*/
|
|
.align 5
|
|
fitint:
|
|
mtsprg 1,1 /* save SP */
|
|
stmw 28,tempsave(0) /* free r28-r31 */
|
|
mflr 28 /* save LR */
|
|
mfcr 29 /* save CR */
|
|
mfxer 30 /* save XER */
|
|
lis 1,intstk+INTSTK@ha /* get interrupt stack */
|
|
addi 1,1,intstk+INTSTK@l
|
|
lwz 31,0(1) /* were we already running on intstk? */
|
|
addic. 31,31,1
|
|
stw 31,0(1)
|
|
beq 1f
|
|
mfsprg 1,1 /* yes, get old SP */
|
|
1:
|
|
INTRENTER
|
|
addi 3,1,8 /* intr frame */
|
|
bl _C_LABEL(stat_intr)
|
|
b intr_exit
|
|
|
|
#ifdef DDB
|
|
/*
|
|
* Deliberate entry to ddbtrap
|
|
*/
|
|
.globl _C_LABEL(ddb_trap)
|
|
_C_LABEL(ddb_trap):
|
|
mtsprg 1,1
|
|
mfmsr 3
|
|
mtsrr1 3
|
|
wrteei 0 /* disable interrupts */
|
|
isync
|
|
stmw 28,ddbsave(0)
|
|
mflr 28
|
|
li 29,EXC_BPT
|
|
mtlr 29
|
|
mfcr 29
|
|
mtsrr0 28
|
|
|
|
/*
|
|
* Now the ddb trap catching code.
|
|
*/
|
|
ddbtrap:
|
|
FRAME_SETUP(ddbsave)
|
|
/* Call C trap code: */
|
|
addi 3,1,8
|
|
bl _C_LABEL(ddb_trap_glue)
|
|
or. 3,3,3
|
|
bne ddbleave
|
|
/* This wasn't for DDB, so switch to real trap: */
|
|
lwz 3,FRAME_EXC+8(1) /* save exception */
|
|
stw 3,ddbsave+12(0)
|
|
FRAME_LEAVE(ddbsave)
|
|
mtsprg 1,1 /* prepare for entrance to realtrap */
|
|
stmw 28,tempsave(0)
|
|
mflr 28
|
|
mfcr 29
|
|
lwz 31,ddbsave+12(0)
|
|
mtlr 31
|
|
b realtrap
|
|
ddbleave:
|
|
FRAME_LEAVE(ddbsave)
|
|
rfi
|
|
ba . /* Protect against prefetch */
|
|
#endif /* DDB */
|
|
|
|
#ifdef IPKDB
|
|
/*
|
|
* Deliberate entry to ipkdbtrap
|
|
*/
|
|
.globl _C_LABEL(ipkdb_trap)
|
|
_C_LABEL(ipkdb_trap):
|
|
mtsprg 1,1
|
|
mfmsr 3
|
|
mtsrr1 3
|
|
wrteei 0 /* disable interrupts */
|
|
isync
|
|
stmw 28,ipkdbsave(0)
|
|
mflr 28
|
|
li 29,EXC_BPT
|
|
mtlr 29
|
|
mfcr 29
|
|
mtsrr0 28
|
|
|
|
/*
|
|
* Now the ipkdb trap catching code.
|
|
*/
|
|
ipkdbtrap:
|
|
FRAME_SETUP(ipkdbsave)
|
|
/* Call C trap code: */
|
|
addi 3,1,8
|
|
bl _C_LABEL(ipkdb_trap_glue)
|
|
or. 3,3,3
|
|
bne ipkdbleave
|
|
/* This wasn't for IPKDB, so switch to real trap: */
|
|
lwz 3,FRAME_EXC+8(1) /* save exception */
|
|
stw 3,ipkdbsave+8(0)
|
|
FRAME_LEAVE(ipkdbsave)
|
|
mtsprg 1,1 /* prepare for entrance to realtrap */
|
|
stmw 28,tempsave(0)
|
|
mflr 28
|
|
mfcr 29
|
|
lwz 31,ipkdbsave+8(0)
|
|
mtlr 31
|
|
b realtrap
|
|
ipkdbleave:
|
|
FRAME_LEAVE(ipkdbsave)
|
|
rfi
|
|
ba . /* Protect against prefetch */
|
|
|
|
ipkdbfault:
|
|
ba _ipkdbfault
|
|
_ipkdbfault:
|
|
mfsrr0 3
|
|
addi 3,3,4
|
|
mtsrr0 3
|
|
li 3,-1
|
|
rfi
|
|
ba . /* Protect against prefetch */
|
|
|
|
/*
|
|
* int ipkdbfbyte(unsigned char *p)
|
|
*/
|
|
.globl _C_LABEL(ipkdbfbyte)
|
|
_C_LABEL(ipkdbfbyte):
|
|
li 9,EXC_DSI /* establish new fault routine */
|
|
lwz 5,0(9)
|
|
lis 6,ipkdbfault@ha
|
|
lwz 6,ipkdbfault@l(6)
|
|
stw 6,0(9)
|
|
#ifdef IPKDBUSERHACK
|
|
#ifndef PPC_IBM4XX
|
|
lis 8,_C_LABEL(ipkdbsr)@ha
|
|
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
|
mtsr USER_SR,8
|
|
isync
|
|
#endif
|
|
#endif
|
|
dcbst 0,9 /* flush data... */
|
|
sync
|
|
icbi 0,9 /* and instruction caches */
|
|
lbz 3,0(3) /* fetch data */
|
|
stw 5,0(9) /* restore previous fault handler */
|
|
dcbst 0,9 /* and flush data... */
|
|
sync
|
|
icbi 0,9 /* and instruction caches */
|
|
blr
|
|
|
|
/*
|
|
* int ipkdbsbyte(unsigned char *p, int c)
|
|
*/
|
|
.globl _C_LABEL(ipkdbsbyte)
|
|
_C_LABEL(ipkdbsbyte):
|
|
li 9,EXC_DSI /* establish new fault routine */
|
|
lwz 5,0(9)
|
|
lis 6,ipkdbfault@ha
|
|
lwz 6,ipkdbfault@l(6)
|
|
stw 6,0(9)
|
|
#ifdef IPKDBUSERHACK
|
|
#ifndef PPC_IBM4XX
|
|
lis 8,_C_LABEL(ipkdbsr)@ha
|
|
lwz 8,_C_LABEL(ipkdbsr)@l(8)
|
|
mtsr USER_SR,8
|
|
isync
|
|
#endif
|
|
#endif
|
|
dcbst 0,9 /* flush data... */
|
|
sync
|
|
icbi 0,9 /* and instruction caches */
|
|
mr 6,3
|
|
xor 3,3,3
|
|
stb 4,0(6)
|
|
dcbst 0,6 /* Now do appropriate flushes
|
|
to data... */
|
|
sync
|
|
icbi 0,6 /* and instruction caches */
|
|
stw 5,0(9) /* restore previous fault handler */
|
|
dcbst 0,9 /* and flush data... */
|
|
sync
|
|
icbi 0,9 /* and instruction caches */
|
|
blr
|
|
#endif /* IPKDB */
|