148 lines
5.0 KiB
Plaintext
148 lines
5.0 KiB
Plaintext
$NetBSD: HPMMU.notes,v 1.2 1994/10/26 07:22:51 cgd Exp $
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Overview:
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--------
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(Some of this is gleaned from an article in the September 1986
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Hewlett-Packard Journal and info in the July 1987 HP Communicator)
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Page and segment table entries mimic the Motorola 68851 PMMU,
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in an effort at upward compatibility. The HP MMU uses a two
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level translation scheme. There are seperate (but equal!)
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translation tables for both supervisor and user modes. At the
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lowest level are page tables. Each page table consists of one
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or more 4k pages of 1024x4 byte page table entries. Each PTE
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maps one 4k page of VA space. At the highest level is the
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segment table. The segment table is a single 4K page of 1024x4
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byte entries. Each entry points to a 4k page of PTEs. Hence
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one STE maps 4Mb of VA space and one page of STEs is sufficient
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to map the entire 4Gb address space (what a coincidence!). The
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unused valid bit in page and segment table entries must be
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zero.
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There are seperate translation lookaside buffers for the user
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and supervisor modes, each containing 1024 entries.
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To augment the 68020's instruction cache, the HP CPU has an
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external cache. A direct-mapped, virtual cache implementation
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is used with 16 Kbytes of cache on 320 systems and 32 Kbytes on
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350 systems. Each cache entry can contain instructions or data,
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from either user or supervisor space. Seperate valid bits are
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kept for user and supervisor entries, allowing for descriminatory
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flushing of the cache.
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MMU translation and cache-miss detection are done in parallel.
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Segment table entries:
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------- ----- -------
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bits 31-12: Physical page frame number of PT page
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bits 11-4: Reserved at zero
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(can software use them?)
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bit 3: Reserved at one
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bit 2: Set to 1 if segment is read-only, ow read-write
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bits 1-0: Valid bits
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(hardware uses bit 1)
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Page table entries:
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---- ----- -------
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bits 31-12: Physical page frame number of page
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bits 11-7: Available for software use
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bit 6: If 1, inhibits caching of data in this page.
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(both instruction and external cache)
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bit 5: Reserved at zero
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bit 4: Hardware modify bit
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bit 3: Hardware reference bit
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bit 2: Set to 1 if page is read-only, ow read-write
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bits 1-0: Valid bits
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(hardware uses bit 0)
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Hardware registers:
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-------- ---------
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The hardware has four longword registers controlling the MMU.
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The registers can be accessed as shortwords also (remember to
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add 2 to addresses given below).
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5F4000: Supervisor mode segment table pointer. Loaded (as longword)
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with page frame number (i.e. Physaddr >> 12) of the segment
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table mapping supervisor space.
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5F4004: User mode segment table pointer. Loaded (as longword) with
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page frame number of the segment table mapping user space.
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5F4008: TLB control register. Used to invalid large sections of the
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TLB. More info below.
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5F400C: MMU command/status register. Defined as follows:
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bit 15: If 1, indicates a page table fault occured
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bit 14: If 1, indicates a page fault occured
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bit 13: If 1, indicates a protection fault (write to RO page)
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bit 6: MC68881 enable. Tied to chip enable line.
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(set this bit to enable)
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bit 5: MC68020 instruction cache enable. Tied to Insruction
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cache disable line. (set this bit to enable)
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bit 3: If 1, indicates an MMU related bus error occured.
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Bits 13-15 are now valid.
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bit 2: External cache enable. (set this bit to enable)
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bit 1: Supervisor mapping enable. Enables translation of
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supervisor space VAs.
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bit 0: User mapping enable. Enables translation of user
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space VAs.
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Any bits set by the hardware are cleared only by software.
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(i.e. bits 3,13,14,15)
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Invalidating TLB:
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------------ ---
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All translations:
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Read the TLB control register (5F4008) as a longword.
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User translations only:
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Write a longword 0 to TLB register or set the user
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segment table pointer.
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Supervisor translations only:
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Write a longword 0x8000 to TLB register or set the
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supervisor segment table pointer.
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A particular VA translation:
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Set destination function code to 3 ("purge" space),
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write a longword 0 to the VA whose translation we are to
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invalidate, and restore function code. This apparently
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invalidates any translation for that VA in both the user
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and supervisor LB. Here is what I did:
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#define FC_PURGE 3
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#define FC_USERD 1
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_TBIS:
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movl sp@(4),a0 | VA to invalidate
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moveq #FC_PURGE,d0 | change address space
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movc d0,dfc | for destination
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moveq #0,d0 | zero to invalidate?
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movsl d0,a0@ | hit it
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moveq #FC_USERD,d0 | back to old
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movc d0,dfc | address space
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rts | done
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Invalidating the external cache:
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------------ --- -------- -----
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Everything:
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Toggle the cache enable bit (bit 2) in the MMU control
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register (5F400C). Can be done by ANDing and ORing the
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register location.
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User:
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Change the user segment table pointer register (5F4004),
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i.e. read the current value and write it back.
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Supervisor:
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Change the supervisor segment table pointer register
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(5F4000), i.e. read the current value and write it back.
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