685 lines
18 KiB
C
685 lines
18 KiB
C
/* $NetBSD: rgephy.c,v 1.59 2020/03/15 23:04:50 thorpej Exp $ */
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/*
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* Copyright (c) 2003
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.59 2020/03/15 23:04:50 thorpej Exp $");
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/*
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* Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/mdio.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <dev/mii/rgephyreg.h>
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#include <dev/ic/rtl81x9reg.h>
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static int rgephy_match(device_t, cfdata_t, void *);
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static void rgephy_attach(device_t, device_t, void *);
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struct rgephy_softc {
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struct mii_softc mii_sc;
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bool mii_no_rx_delay;
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};
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CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc),
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rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate);
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static int rgephy_service(struct mii_softc *, struct mii_data *, int);
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static void rgephy_status(struct mii_softc *);
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static int rgephy_mii_phy_auto(struct mii_softc *);
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static void rgephy_reset(struct mii_softc *);
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static bool rgephy_linkup(struct mii_softc *);
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static void rgephy_loop(struct mii_softc *);
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static void rgephy_load_dspcode(struct mii_softc *);
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static const struct mii_phy_funcs rgephy_funcs = {
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rgephy_service, rgephy_status, rgephy_reset,
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};
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static const struct mii_phydesc rgephys[] = {
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MII_PHY_DESC(xxREALTEK, RTL8169S),
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MII_PHY_DESC(REALTEK, RTL8169S),
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MII_PHY_DESC(REALTEK, RTL8251),
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MII_PHY_END,
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};
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static int
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rgephy_match(device_t parent, cfdata_t match, void *aux)
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{
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struct mii_attach_args *ma = aux;
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if (mii_phy_match(ma, rgephys) != NULL)
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return 10;
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return 0;
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}
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static void
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rgephy_attach(device_t parent, device_t self, void *aux)
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{
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struct rgephy_softc *rsc = device_private(self);
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prop_dictionary_t prop = device_properties(self);
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struct mii_softc *sc = &rsc->mii_sc;
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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const struct mii_phydesc *mpd;
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mpd = mii_phy_match(ma, rgephys);
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aprint_naive(": Media interface\n");
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sc->mii_dev = self;
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_funcs = &rgephy_funcs;
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sc->mii_pdata = mii;
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sc->mii_flags = ma->mii_flags;
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sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
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sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
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sc->mii_mpd_rev = MII_REV(ma->mii_id2);
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if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8169S) {
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aprint_normal(": RTL8211");
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if (sc->mii_mpd_rev != 0)
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aprint_normal("%c",'@' + sc->mii_mpd_rev);
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aprint_normal(" 1000BASE-T media interface\n");
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} else {
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aprint_normal(": %s, rev. %d\n", mpd->mpd_name,
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sc->mii_mpd_rev);
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}
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prop_dictionary_get_bool(prop, "no-rx-delay", &rsc->mii_no_rx_delay);
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#ifdef __FreeBSD__
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
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BMCR_LOOP | BMCR_S100);
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#endif
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mii_lock(mii);
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PHY_RESET(sc);
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PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
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sc->mii_capabilities &= ma->mii_capmask;
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/* RTL8169S does not report auto-sense; add manually. */
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sc->mii_capabilities |= BMSR_ANEG;
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/*
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* FreeBSD does not check EXSTAT, but instead adds gigabit
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* media explicitly. Why?
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*/
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
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mii_unlock(mii);
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mii_phy_add_media(sc);
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}
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static int
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rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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uint16_t reg, speed, gig, anar;
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KASSERT(mii_locked(mii));
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switch (cmd) {
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case MII_POLLSTAT:
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/* If we're not polling our PHY instance, just return. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return 0;
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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PHY_READ(sc, MII_BMCR, ®);
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PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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return 0;
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}
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/* If the interface is not up, don't do anything. */
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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rgephy_reset(sc); /* XXX hardware bug work-around */
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PHY_READ(sc, MII_ANAR, &anar);
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anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10);
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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#ifdef foo
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/* If we're already in auto mode, just return. */
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PHY_READ(sc, MII_BMCR, ®);
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if (reg & BMCR_AUTOEN)
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return 0;
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#endif
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(void)rgephy_mii_phy_auto(sc);
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break;
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case IFM_1000_T:
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speed = BMCR_S1000;
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goto setit;
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case IFM_100_TX:
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speed = BMCR_S100;
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anar |= ANAR_TX_FD | ANAR_TX;
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goto setit;
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case IFM_10_T:
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speed = BMCR_S10;
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anar |= ANAR_10_FD | ANAR_10;
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setit:
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rgephy_loop(sc);
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if ((ife->ifm_media & IFM_FDX) != 0) {
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speed |= BMCR_FDX;
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gig = GTCR_ADV_1000TFDX;
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anar &= ~(ANAR_TX | ANAR_10);
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} else {
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gig = GTCR_ADV_1000THDX;
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anar &= ~(ANAR_TX_FD | ANAR_10_FD);
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}
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) {
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PHY_WRITE(sc, MII_100T2CR, 0);
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PHY_WRITE(sc, MII_ANAR, anar);
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PHY_WRITE(sc, MII_BMCR,
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speed | BMCR_AUTOEN | BMCR_STARTNEG);
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break;
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}
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/*
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* When setting the link manually, one side must be the
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* master and the other the slave. However ifmedia
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* doesn't give us a good way to specify this, so we
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* fake it by using one of the LINK flags. If LINK0 is
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* set, we program the PHY to be a master, otherwise
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* it's a slave.
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*/
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if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
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PHY_WRITE(sc, MII_100T2CR,
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gig | GTCR_MAN_MS | GTCR_ADV_MS);
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} else
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PHY_WRITE(sc, MII_100T2CR, gig | GTCR_MAN_MS);
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PHY_WRITE(sc, MII_BMCR,
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speed | BMCR_AUTOEN | BMCR_STARTNEG);
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break;
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case IFM_NONE:
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PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
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break;
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case IFM_100_T4:
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default:
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return EINVAL;
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}
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break;
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case MII_TICK:
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/* If we're not currently selected, just return. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return 0;
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/* Is the interface even up? */
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return 0;
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/* Only used for autonegotiation. */
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if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) &&
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(IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) {
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/*
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* Reset autonegotiation timer to 0 to make sure
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* the future autonegotiation start with 0.
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*/
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sc->mii_ticks = 0;
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break;
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}
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process. Read
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* the BMSR twice in case it's latched.
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*/
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if (rgephy_linkup(sc)) {
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sc->mii_ticks = 0;
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break;
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}
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/* Announce link loss right after it happens. */
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if (sc->mii_ticks++ == 0)
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break;
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/* Only retry autonegotiation every mii_anegticks seconds. */
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if (sc->mii_ticks <= sc->mii_anegticks)
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return 0;
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rgephy_mii_phy_auto(sc);
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break;
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}
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/* Update the media status. */
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rgephy_status(sc);
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/*
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* Callback if something changed. Note that we need to poke
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* the DSP on the RealTek PHYs if the media changes.
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*/
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if (sc->mii_media_active != mii->mii_media_active ||
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sc->mii_media_status != mii->mii_media_status ||
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cmd == MII_MEDIACHG) {
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rgephy_load_dspcode(sc);
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}
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mii_phy_update(sc, cmd);
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return 0;
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}
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static bool
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rgephy_linkup(struct mii_softc *sc)
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{
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bool linkup = false;
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uint16_t reg;
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if (sc->mii_mpd_rev >= RGEPHY_8211F) {
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PHY_READ(sc, RGEPHY_MII_PHYSR, ®);
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if (reg & RGEPHY_PHYSR_LINK)
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linkup = true;
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} else if (sc->mii_mpd_rev >= RGEPHY_8211B) {
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PHY_READ(sc, RGEPHY_MII_SSR, ®);
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if (reg & RGEPHY_SSR_LINK)
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linkup = true;
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} else {
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PHY_READ(sc, RTK_GMEDIASTAT, ®);
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if ((reg & RTK_GMEDIASTAT_LINK) != 0)
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linkup = true;
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}
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return linkup;
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}
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static void
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rgephy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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uint16_t gstat, bmsr, bmcr, gtsr, physr, ssr;
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KASSERT(mii_locked(mii));
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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if (rgephy_linkup(sc))
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mii->mii_media_status |= IFM_ACTIVE;
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PHY_READ(sc, MII_BMSR, &bmsr);
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PHY_READ(sc, MII_BMCR, &bmcr);
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if ((bmcr & BMCR_ISO) != 0) {
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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if ((bmcr & BMCR_LOOP) != 0)
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mii->mii_media_active |= IFM_LOOP;
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if ((bmcr & BMCR_AUTOEN) != 0) {
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if ((bmsr & BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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}
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if (sc->mii_mpd_rev >= RGEPHY_8211F) {
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PHY_READ(sc, RGEPHY_MII_PHYSR, &physr);
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switch (__SHIFTOUT(physr, RGEPHY_PHYSR_SPEED)) {
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case RGEPHY_PHYSR_SPEED_1000:
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mii->mii_media_active |= IFM_1000_T;
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break;
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case RGEPHY_PHYSR_SPEED_100:
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mii->mii_media_active |= IFM_100_TX;
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break;
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case RGEPHY_PHYSR_SPEED_10:
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mii->mii_media_active |= IFM_10_T;
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break;
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default:
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mii->mii_media_active |= IFM_NONE;
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break;
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}
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if (physr & RGEPHY_PHYSR_DUPLEX)
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mii->mii_media_active |= mii_phy_flowstatus(sc) |
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IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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} else if (sc->mii_mpd_rev >= RGEPHY_8211B) {
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PHY_READ(sc, RGEPHY_MII_SSR, &ssr);
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switch (ssr & RGEPHY_SSR_SPD_MASK) {
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case RGEPHY_SSR_S1000:
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mii->mii_media_active |= IFM_1000_T;
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break;
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case RGEPHY_SSR_S100:
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mii->mii_media_active |= IFM_100_TX;
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break;
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case RGEPHY_SSR_S10:
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mii->mii_media_active |= IFM_10_T;
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break;
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default:
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mii->mii_media_active |= IFM_NONE;
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break;
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}
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if (ssr & RGEPHY_SSR_FDX)
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mii->mii_media_active |= mii_phy_flowstatus(sc) |
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IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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} else {
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PHY_READ(sc, RTK_GMEDIASTAT, &gstat);
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if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0)
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mii->mii_media_active |= IFM_1000_T;
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else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0)
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mii->mii_media_active |= IFM_100_TX;
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else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0)
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mii->mii_media_active |= IFM_10_T;
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else
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mii->mii_media_active |= IFM_NONE;
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if ((gstat & RTK_GMEDIASTAT_FDX) != 0)
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mii->mii_media_active |= mii_phy_flowstatus(sc) |
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IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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}
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if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
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PHY_READ(sc, MII_GTSR, >sr);
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if ((gtsr & GTSR_MS_RES) != 0)
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mii->mii_media_active |= IFM_ETH_MASTER;
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}
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}
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static int
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rgephy_mii_phy_auto(struct mii_softc *mii)
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{
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int anar;
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mii->mii_ticks = 0;
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rgephy_loop(mii);
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rgephy_reset(mii);
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anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA;
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if (mii->mii_flags & MIIF_DOPAUSE)
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anar |= ANAR_FC | ANAR_PAUSE_ASYM;
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PHY_WRITE(mii, MII_ANAR, anar);
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DELAY(1000);
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PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX);
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DELAY(1000);
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PHY_WRITE(mii, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
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DELAY(100);
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return EJUSTRETURN;
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}
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static void
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rgephy_loop(struct mii_softc *sc)
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{
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uint16_t bmsr;
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int i;
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if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 &&
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sc->mii_mpd_rev < RGEPHY_8211B) {
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PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN);
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DELAY(1000);
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}
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for (i = 0; i < 15000; i++) {
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PHY_READ(sc, MII_BMSR, &bmsr);
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if ((bmsr & BMSR_LINK) == 0) {
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#if 0
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device_printf(sc->mii_dev, "looped %d\n", i);
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#endif
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break;
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}
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DELAY(10);
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}
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}
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|
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static inline int
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PHY_SETBIT(struct mii_softc *sc, int y, uint16_t z)
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{
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uint16_t _tmp;
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int rv;
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if ((rv = PHY_READ(sc, y, &_tmp)) != 0)
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return rv;
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return PHY_WRITE(sc, y, _tmp | z);
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}
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|
|
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static inline int
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PHY_CLRBIT(struct mii_softc *sc, int y, uint16_t z)
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{
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uint16_t _tmp;
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int rv;
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|
|
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if ((rv = PHY_READ(sc, y, &_tmp)) != 0)
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return rv;
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return PHY_WRITE(sc, y, _tmp & ~z);
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}
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|
|
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/*
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* Initialize RealTek PHY per the datasheet. The DSP in the PHYs of existing
|
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* revisions of the 8169S/8110S chips need to be tuned in order to reliably
|
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* negotiate a 1000Mbps link. This is only needed for rev 0 and rev 1 of the
|
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* PHY. Later versions work without any fixups.
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*/
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static void
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rgephy_load_dspcode(struct mii_softc *sc)
|
|
{
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uint16_t val;
|
|
|
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if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 ||
|
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sc->mii_mpd_rev >= RGEPHY_8211B)
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return;
|
|
|
|
#if 1
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PHY_WRITE(sc, 31, 0x0001);
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PHY_WRITE(sc, 21, 0x1000);
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PHY_WRITE(sc, 24, 0x65C7);
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PHY_CLRBIT(sc, 4, 0x0800);
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PHY_READ(sc, 4, &val);
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val &= 0xFFF;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0x00A1);
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PHY_WRITE(sc, 2, 0x0008);
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PHY_WRITE(sc, 1, 0x1020);
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PHY_WRITE(sc, 0, 0x1000);
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PHY_SETBIT(sc, 4, 0x0800);
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PHY_CLRBIT(sc, 4, 0x0800);
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PHY_READ(sc, 4, &val);
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val = (val & 0xFFF) | 0x7000;
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PHY_WRITE(sc, 4, val);
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PHY_WRITE(sc, 3, 0xFF41);
|
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PHY_WRITE(sc, 2, 0xDE60);
|
|
PHY_WRITE(sc, 1, 0x0140);
|
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PHY_WRITE(sc, 0, 0x0077);
|
|
PHY_READ(sc, 4, &val);
|
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val = (val & 0xFFF) | 0xA000;
|
|
PHY_WRITE(sc, 4, val);
|
|
PHY_WRITE(sc, 3, 0xDF01);
|
|
PHY_WRITE(sc, 2, 0xDF20);
|
|
PHY_WRITE(sc, 1, 0xFF95);
|
|
PHY_WRITE(sc, 0, 0xFA00);
|
|
PHY_READ(sc, 4, &val);
|
|
val = (val & 0xFFF) | 0xB000;
|
|
PHY_WRITE(sc, 4, val);
|
|
PHY_WRITE(sc, 3, 0xFF41);
|
|
PHY_WRITE(sc, 2, 0xDE20);
|
|
PHY_WRITE(sc, 1, 0x0140);
|
|
PHY_WRITE(sc, 0, 0x00BB);
|
|
PHY_READ(sc, 4, &val);
|
|
val = (val & 0xFFF) | 0xF000;
|
|
PHY_WRITE(sc, 4, val);
|
|
PHY_WRITE(sc, 3, 0xDF01);
|
|
PHY_WRITE(sc, 2, 0xDF20);
|
|
PHY_WRITE(sc, 1, 0xFF95);
|
|
PHY_WRITE(sc, 0, 0xBF00);
|
|
PHY_SETBIT(sc, 4, 0x0800);
|
|
PHY_CLRBIT(sc, 4, 0x0800);
|
|
PHY_WRITE(sc, 31, 0x0000);
|
|
#else
|
|
(void)val;
|
|
PHY_WRITE(sc, 0x1f, 0x0001);
|
|
PHY_WRITE(sc, 0x15, 0x1000);
|
|
PHY_WRITE(sc, 0x18, 0x65c7);
|
|
PHY_WRITE(sc, 0x04, 0x0000);
|
|
PHY_WRITE(sc, 0x03, 0x00a1);
|
|
PHY_WRITE(sc, 0x02, 0x0008);
|
|
PHY_WRITE(sc, 0x01, 0x1020);
|
|
PHY_WRITE(sc, 0x00, 0x1000);
|
|
PHY_WRITE(sc, 0x04, 0x0800);
|
|
PHY_WRITE(sc, 0x04, 0x0000);
|
|
PHY_WRITE(sc, 0x04, 0x7000);
|
|
PHY_WRITE(sc, 0x03, 0xff41);
|
|
PHY_WRITE(sc, 0x02, 0xde60);
|
|
PHY_WRITE(sc, 0x01, 0x0140);
|
|
PHY_WRITE(sc, 0x00, 0x0077);
|
|
PHY_WRITE(sc, 0x04, 0x7800);
|
|
PHY_WRITE(sc, 0x04, 0x7000);
|
|
PHY_WRITE(sc, 0x04, 0xa000);
|
|
PHY_WRITE(sc, 0x03, 0xdf01);
|
|
PHY_WRITE(sc, 0x02, 0xdf20);
|
|
PHY_WRITE(sc, 0x01, 0xff95);
|
|
PHY_WRITE(sc, 0x00, 0xfa00);
|
|
PHY_WRITE(sc, 0x04, 0xa800);
|
|
PHY_WRITE(sc, 0x04, 0xa000);
|
|
PHY_WRITE(sc, 0x04, 0xb000);
|
|
PHY_WRITE(sc, 0x0e, 0xff41);
|
|
PHY_WRITE(sc, 0x02, 0xde20);
|
|
PHY_WRITE(sc, 0x01, 0x0140);
|
|
PHY_WRITE(sc, 0x00, 0x00bb);
|
|
PHY_WRITE(sc, 0x04, 0xb800);
|
|
PHY_WRITE(sc, 0x04, 0xb000);
|
|
PHY_WRITE(sc, 0x04, 0xf000);
|
|
PHY_WRITE(sc, 0x03, 0xdf01);
|
|
PHY_WRITE(sc, 0x02, 0xdf20);
|
|
PHY_WRITE(sc, 0x01, 0xff95);
|
|
PHY_WRITE(sc, 0x00, 0xbf00);
|
|
PHY_WRITE(sc, 0x04, 0xf800);
|
|
PHY_WRITE(sc, 0x04, 0xf000);
|
|
PHY_WRITE(sc, 0x04, 0x0000);
|
|
PHY_WRITE(sc, 0x1f, 0x0000);
|
|
PHY_WRITE(sc, 0x0b, 0x0000);
|
|
|
|
#endif
|
|
|
|
DELAY(40);
|
|
}
|
|
|
|
static void
|
|
rgephy_reset(struct mii_softc *sc)
|
|
{
|
|
struct rgephy_softc *rsc = (struct rgephy_softc *)sc;
|
|
uint16_t ssr, phycr1;
|
|
|
|
KASSERT(mii_locked(sc->mii_pdata));
|
|
|
|
mii_phy_reset(sc);
|
|
DELAY(1000);
|
|
|
|
if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 &&
|
|
sc->mii_mpd_rev < RGEPHY_8211B) {
|
|
rgephy_load_dspcode(sc);
|
|
} else if (sc->mii_mpd_rev == RGEPHY_8211C) {
|
|
/* RTL8211C(L) */
|
|
PHY_READ(sc, RGEPHY_MII_SSR, &ssr);
|
|
if ((ssr & RGEPHY_SSR_ALDPS) != 0) {
|
|
ssr &= ~RGEPHY_SSR_ALDPS;
|
|
PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
|
|
}
|
|
} else if (sc->mii_mpd_rev == RGEPHY_8211E) {
|
|
/* RTL8211E */
|
|
if (rsc->mii_no_rx_delay) {
|
|
/* Disable RX internal delay (undocumented) */
|
|
PHY_WRITE(sc, 0x1f, 0x0007);
|
|
PHY_WRITE(sc, 0x1e, 0x00a4);
|
|
PHY_WRITE(sc, 0x1c, 0xb591);
|
|
PHY_WRITE(sc, 0x1f, 0x0000);
|
|
}
|
|
} else if (sc->mii_mpd_rev == RGEPHY_8211F) {
|
|
/* RTL8211F */
|
|
PHY_READ(sc, RGEPHY_MII_PHYCR1, &phycr1);
|
|
phycr1 &= ~RGEPHY_PHYCR1_MDI_MMCE;
|
|
phycr1 &= ~RGEPHY_PHYCR1_ALDPS_EN;
|
|
PHY_WRITE(sc, RGEPHY_MII_PHYCR1, phycr1);
|
|
} else {
|
|
PHY_WRITE(sc, 0x1F, 0x0000);
|
|
PHY_WRITE(sc, 0x0e, 0x0000);
|
|
}
|
|
|
|
/* Reset capabilities */
|
|
/* Step1: write our capability */
|
|
/* 10/100 capability */
|
|
PHY_WRITE(sc, MII_ANAR,
|
|
ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
|
|
/* 1000 capability */
|
|
PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX);
|
|
|
|
/* Step2: Restart NWay */
|
|
/* NWay enable and Restart NWay */
|
|
PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
|
|
|
|
if (sc->mii_mpd_rev >= RGEPHY_8211D) {
|
|
/* RTL8211F */
|
|
delay(10000);
|
|
/* disable EEE */
|
|
MMD_INDIRECT_WRITE(sc, MDIO_MMD_AN | MMDACR_FN_DATA,
|
|
MDIO_AN_EEEADVERT, 0x0000);
|
|
}
|
|
}
|