378 lines
14 KiB
C
378 lines
14 KiB
C
/* $NetBSD: ssdfbvar.h,v 1.10 2021/08/05 22:31:20 tnn Exp $ */
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/*
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* Copyright (c) 2019 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tobias Nygren.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* cfdata attachment flags
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*/
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#define SSDFB_ATTACH_FLAG_PRODUCT_MASK 0x000000ff
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#define SSDFB_ATTACH_FLAG_UPSIDEDOWN 0x00000100
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#define SSDFB_ATTACH_FLAG_INVERSE 0x00000200
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#define SSDFB_ATTACH_FLAG_CONSOLE 0x00000400
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#define SSDFB_ATTACH_FLAG_MPSAFE 0x00000800
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/*
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* Fundamental commands
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* SSD1306 Rev 1.1 p.28
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* SH1106 Rev 0.1 p.19,20,22
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*/
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#define SSDFB_CMD_SET_CONTRAST_CONTROL 0x81
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#define SSDFB_CMD_ENTIRE_DISPLAY_OFF 0xa4
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#define SSDFB_CMD_ENTIRE_DISPLAY_ON 0xa5
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#define SSDFB_CMD_SET_NORMAL_DISPLAY 0xa6
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#define SSDFB_CMD_SET_INVERSE_DISPLAY 0xa7
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#define SSDFB_CMD_SET_DISPLAY_OFF 0xae
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#define SSDFB_CMD_SET_DISPLAY_ON 0xaf
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/*
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* Scrolling commands; SSD1306 Rev 1.1 p. 28
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*/
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#define SSDFB_CMD_VERTICAL_AND_RIGHT_SCROLL 0x29
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#define SSDFB_CMD_VERTICAL_AND_LEFT_SCROLL 0x2a
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#define SSDFB_CMD_DEACTIVATE_SCROLL 0x2e
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#define SSDFB_CMD_ACTIVATE_SCROLL 0x2f
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#define SSDFB_CMD_SET_VERTICAL_SCROLL_AREA 0xa3
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/*
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* Addressing commands
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* SSD1306 Rev 1.1 p.30
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* SH1106 Rev 0.1 p.18,22
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*/
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#define SSDFB_CMD_SET_LOWER_COLUMN_START_ADDRESS_BASE 0x00
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#define SSDFB_CMD_SET_LOWER_COLUMN_START_ADDRESS_MAX 0x0f
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#define SSDFB_CMD_SET_HIGHER_COLUMN_START_ADDRESS_BASE 0x10
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#define SSDFB_CMD_SET_HIGHER_COLUMN_START_ADDRESS_MAX 0x1f
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#define SSD1306_CMD_SET_MEMORY_ADDRESSING_MODE 0x20
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#define SSD1306_MEMORY_ADDRESSING_MODE_HORIZONTAL 0x00
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#define SSD1306_MEMORY_ADDRESSING_MODE_VERTICAL 0x01
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#define SSD1306_MEMORY_ADDRESSING_MODE_PAGE 0x02
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#define SSD1306_CMD_SET_COLUMN_ADDRESS 0x21
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#define SSD1306_CMD_SET_PAGE_ADDRESS 0x22
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#define SSDFB_CMD_SET_PAGE_START_ADDRESS_BASE 0xb0
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#define SSDFB_CMD_SET_PAGE_START_ADDRESS_MAX 0xb7
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/*
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* Resolution & hardware layout commands
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* SSD1306 Rev 1.1 p.31
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* SH1106 Rev 0.1 p.19,20,21,23
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*/
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#define SSDFB_CMD_SET_DISPLAY_START_LINE_BASE 0x40
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#define SSDFB_CMD_SET_DISPLAY_START_LINE_MAX 0x7f
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#define SSDFB_CMD_SET_SEGMENT_REMAP_NORMAL 0xa0
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#define SSDFB_CMD_SET_SEGMENT_REMAP_REVERSE 0xa1
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#define SSDFB_CMD_SET_MULTIPLEX_RATIO 0xa8
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#define SSDFB_CMD_SET_COM_OUTPUT_DIRECTION_NORMAL 0xc0
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#define SSDFB_CMD_SET_COM_OUTPUT_DIRECTION_REMAP 0xc8
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#define SSDFB_CMD_SET_DISPLAY_OFFSET 0xd3
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#define SSDFB_CMD_SET_COM_PINS_HARDWARE_CFG 0xda
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#define SSDFB_COM_PINS_A1_MASK 0x02
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#define SSDFB_COM_PINS_ALTERNATIVE_MASK 0x10
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#define SSDFB_COM_PINS_REMAP_MASK 0x20
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/*
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* Timing & driving commands
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* SSD1306 Rev 1.1 p.32
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* SH1106 Rev 0.1 p.24,25,26
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*/
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#define SSDFB_CMD_SET_DISPLAY_CLOCK_RATIO 0xd5
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#define SSDFB_DISPLAY_CLOCK_DIVIDER_MASK __BITS(3, 0)
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#define SSDFB_DISPLAY_CLOCK_OSCILLATOR_MASK __BITS(7, 4)
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#define SSDFB_CMD_SET_PRECHARGE_PERIOD 0xd9
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#define SSDFB_PRECHARGE_MASK __BITS(3, 0)
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#define SSDFB_DISCHARGE_MASK __BITS(7, 4)
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#define SSDFB_CMD_SET_VCOMH_DESELECT_LEVEL 0xdb
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#define SSD1306_VCOMH_DESELECT_LEVEL_0_65_VCC 0x00
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#define SSD1306_VCOMH_DESELECT_LEVEL_0_77_VCC 0x20
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#define SSD1306_VCOMH_DESELECT_LEVEL_0_83_VCC 0x30
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#define SH1106_VCOMH_DESELECT_LEVEL_DEFAULT 0x35
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/*
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* Misc commands
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* SSD1306 Rev 1.1 p.32
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* SH1106 Rev 0.1 p.27,28
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*/
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#define SSDFB_CMD_NOP 0xe3
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#define SH1106_CMD_READ_MODIFY_WRITE 0xe0
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#define SH1106_CMD_READ_MODIFY_WRITE_CANCEL 0xee
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/*
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* Charge pump commands
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* SSD1306 App Note Rev 0.4 p.3
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* SH1106 V0.1 p.18
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*/
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#define SSD1306_CMD_SET_CHARGE_PUMP 0x8d
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#define SSD1306_CHARGE_PUMP_ENABLE 0x14
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#define SSD1306_CHARGE_PUMP_DISABE 0x10
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#define SH1106_CMD_SET_CHARGE_PUMP_7V4 0x30
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#define SH1106_CMD_SET_CHARGE_PUMP_8V0 0x31
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#define SH1106_CMD_SET_CHARGE_PUMP_8V4 0x32
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#define SH1106_CMD_SET_CHARGE_PUMP_9V0 0x33
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/*
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* DC-DC commands
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* SH1106 V0.1 p.18
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*/
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#define SH1106_CMD_SET_DC_DC 0xad
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#define SH1106_DC_DC_OFF 0x8a
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#define SH1106_DC_DC_ON 0x8b
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/*
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* SSD1322 command set
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*/
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#define SSD1322_CMD_ENABLE_GRAY_SCALE_TABLE 0x00
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#define SSD1322_CMD_SET_COLUMN_ADDRESS 0x15
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#define SSD1322_CMD_WRITE_RAM 0x5c
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#define SSD1322_CMD_READ_RAM 0x5d
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#define SSD1322_CMD_SET_ROW_ADDRESS 0x75
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#define SSD1322_CMD_SET_REMAP_AND_DUAL_COM_LINE_MODE 0xa0
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#define SSD1322_CMD_SET_DISPLAY_START_LINE 0xa1
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#define SSD1322_CMD_SET_DISPLAY_OFFSET 0xa2
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#define SSD1322_CMD_ENTIRE_DISPLAY_OFF SSDFB_CMD_ENTIRE_DISPLAY_OFF
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#define SSD1322_CMD_ENTIRE_DISPLAY_ON SSDFB_CMD_ENTIRE_DISPLAY_ON
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#define SSD1322_CMD_NORMAL_DISPLAY SSDFB_CMD_SET_NORMAL_DISPLAY
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#define SSD1322_CMD_INVERSE_DISPLAY SSDFB_CMD_SET_INVERSE_DISPLAY
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#define SSD1322_CMD_SET_SLEEP_MODE_ON SSDFB_CMD_SET_DISPLAY_OFF
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#define SSD1322_CMD_SET_SLEEP_MODE_OFF SSDFB_CMD_SET_DISPLAY_ON
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#define SSD1322_CMD_ENABLE_PARTIAL_DISPLAY 0xa8
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#define SSD1322_CMD_EXIT_PARTIAL_DISPLAY 0xa9
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#define SSD1322_CMD_FUNCTION_SELECTION 0xab
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#define SSD1322_FUNCTION_SELECTION_EXTERNAL_VDD 0
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#define SSD1322_FUNCTION_SELECTION_INTERNAL_VDD __BIT(0)
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#define SSD1322_CMD_SET_PHASE_LENGTH 0xb1
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#define SSD1322_PHASE_LENGTH_PHASE_2_MASK __BITS(7, 4)
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#define SSD1322_DEFAULT_PHASE_2 7
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#define SSD1322_PHASE_LENGTH_PHASE_1_MASK __BITS(3, 0)
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#define SSD1322_DEFAULT_PHASE_1 4
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#define SSD1322_CMD_SET_FRONT_CLOCK_DIVIDER 0xb3
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#define SSD1322_FREQUENCY_MASK __BITS(7, 4)
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#define SSD1322_DEFAULT_FREQUENCY 5
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#define SSD1322_DIVIDER_MASK __BITS(3, 0)
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#define SSD1322_DEFAULT_DIVIDER 0
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#define SSD1322_CMD_DISPLAY_ENHANCEMENT_A 0xb4
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#define SSD1322_DISPLAY_ENHANCEMENT_A_MAGIC1 0xa2
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#define SSD1322_DISPLAY_ENHANCEMENT_A_MAGIC2 0xb5
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#define SSD1322_CMD_SET_GPIO 0xb5
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#define SSD1322_GPIO0_DISABLED 0
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#define SSD1322_GPIO0_TRISTATE __BIT(0)
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#define SSD1322_GPIO0_LOW __BIT(1)
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#define SSD1322_GPIO0_HIGH __BITS(1, 0)
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#define SSD1322_GPIO1_DISABLED 0
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#define SSD1322_GPIO1_TRISTATE __BIT(2)
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#define SSD1322_GPIO1_LOW __BIT(3)
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#define SSD1322_GPIO1_HIGH __BITS(3, 2)
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#define SSD1322_CMD_SET_SECOND_PRECHARGE_PERIOD 0xb6
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#define SSD1322_DEFAULT_SECOND_PRECHARGE_PERIOD 8
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#define SSD1322_CMD_SET_GRAY_SCALE_TABLE 0xb8
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#define SSD1322_CMD_SET_DEFAULT_GRAY_SCALE_TABLE 0xb9
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#define SSD1322_CMD_SET_PRE_CHARGE_VOLTAGE_LEVEL 0xbb
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#define SSD1322_DEFAULT_PRE_CHARGE_VOLTAGE_LEVEL 0x17
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#define SSD1322_CMD_SET_VCOMH 0xbe
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#define SSD1322_DEFAULT_VCOMH 0x04
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#define SSD1322_CMD_SET_CONTRAST_CURRENT 0xc1
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#define SSD1322_DEFAULT_CONTRAST_CURRENT 0x7f
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#define SSD1322_CMD_MASTER_CONTRAST_CURRENT_CONTROL 0xc7
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#define SSD1322_DEFAULT_MASTER_CONTRAST_CURRENT_CONTROL 0xf
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#define SSD1322_CMD_SET_MULTIPLEX_RATIO 0xca
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#define SSD1322_CMD_DISPLAY_ENHANCEMENT_B 0xd1
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#define SSD1322_DISPLAY_ENHANCEMENT_B_MAGIC1 0xa2
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#define SSD1322_DISPLAY_ENHANCEMENT_B_MAGIC2 0x20
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#define SSD1322_CMD_SET_COMMAND_LOCK 0xfd
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#define SSD1322_COMMAND_UNLOCK_MAGIC 0x12
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#define SSD1322_COMMAND_LOCK_MAGIC 0x16
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/* undocumented on this chip, but works in practice */
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#define SSD1322_CMD_NOP SSDFB_CMD_NOP
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/*
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* SSD1353 command set
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*/
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#define SSD1353_CMD_SET_COLUMN_ADDRESS SSD1322_CMD_SET_COLUMN_ADDRESS
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#define SSD1353_CMD_DRAW_LINE 0x21
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#define SSD1353_CMD_DRAW_RECTANGLE 0x22
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#define SSD1353_CMD_COPY 0x23
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#define SSD1353_CMD_DIM 0x24
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#define SSD1353_CMD_CLEAR_WINDOW 0x25
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#define SSD1353_CMD_FILL_ENABLE 0x26
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#define SSD1353_CMD_SCROLLING_SETUP 0x27
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#define SSD1353_CMD_DEACTIVATE_SCROLL SSDFB_CMD_DEACTIVATE_SCROLL
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#define SSD1353_CMD_ACTIVATE_SCROLL SSDFB_CMD_ACTIVATE_SCROLL
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#define SSD1353_CMD_WRITE_RAM SSD1322_CMD_WRITE_RAM
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#define SD1353_CMD_READ_RAM SSD1322_CMD_READ_RAM
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#define SSD1353_CMD_SET_ROW_ADDRESS SSD1322_CMD_SET_ROW_ADDRESS
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#define SSD1353_CMD_SET_CONTRAST_CONTROL_A 0x81
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#define SSD1353_CMD_SET_CONTRAST_CONTROL_B 0x82
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#define SSD1353_CMD_SET_CONTRAST_CONTROL_C 0x83
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#define SSD1353_DEFAULT_CONTRAST_CONTROL 128
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#define SSD1353_CMD_MASTER_CURRENT_CONTROL 0x87
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#define SSD1353_DEFAULT_MASTER_CURRENT_ATTENUATION 15
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#define SSD1353_CMD_SET_SECOND_PRECHARGE_SPEED 0x8a
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#define SSD1353_DEFAULT_SECOND_PRECHARGE_SPEED 2
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#define SSD1353_CMD_REMAP_COLOR_DEPTH 0xa0
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#define SSD1353_REMAP_NO_INCREMENT __BIT(0)
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#define SSD1353_REMAP_SEG_DIRECTION __BIT(1)
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#define SSD1353_REMAP_RGB __BIT(2)
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#define SSD1353_REMAP_LR __BIT(3)
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#define SSD1353_REMAP_COM_DIRECTION __BIT(4)
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#define SSD1353_REMAP_SPLIT_ODD_EVEN __BIT(5)
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#define SSD1353_REMAP_PIXEL_FORMAT_MASK __BITS(7, 6)
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#define SSD1353_CMD_SET_DISPLAY_START_LINE SSD1322_CMD_SET_DISPLAY_START_LINE
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#define SSD1353_CMD_SET_DISPLAY_OFFSET SSD1322_CMD_SET_DISPLAY_OFFSET
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#define SSD1353_CMD_SET_VERTICAL_SCROLL_AREA SSDFB_CMD_SET_VERTICAL_SCROLL_AREA
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#define SSD1353_CMD_NORMAL_DISPLAY 0xa4
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#define SSD1353_CMD_ENTIRE_DISPLAY_ON 0xa5
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#define SSD1353_CMD_ENTIRE_DISPLAY_OFF 0xa6
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#define SSD1353_CMD_INVERSE_DISPLAY SSDFB_CMD_SET_INVERSE_DISPLAY
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#define SSD1353_CMD_SET_MULTIPLEX_RATIO SSDFB_CMD_SET_MULTIPLEX_RATIO
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#define SSD1353_CMD_DIM_MODE_SETTING 0xab
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#define SSD1353_CMD_SET_DISPLAY_ON_DIM 0xac
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#define SSD1353_CMD_SET_DISPLAY_OFF SSDFB_CMD_SET_DISPLAY_OFF
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#define SSD1353_CMD_SET_DISPLAY_ON SSDFB_CMD_SET_DISPLAY_ON
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#define SSD1353_CMD_SET_PHASE_LENGTH SSD1322_CMD_SET_PHASE_LENGTH
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#define SSD1353_DEFAULT_PHASE_2 7
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#define SSD1353_DEFAULT_PHASE_1 4
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#define SSD1353_CMD_SET_FRONT_CLOCK_DIVIDER SSD1322_CMD_SET_FRONT_CLOCK_DIVIDER
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#define SSD1353_DEFAULT_DIVIDER 0
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#define SSD1353_DEFAULT_FREQUENCY 12
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#define SSD1353_CMD_SET_SECOND_PRECHARGE_PERIOD 0xb4
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#define SSD1353_DEFAULT_SECOND_PRECHARGE_PERIOD 7
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#define SSD1353_CMD_SET_GRAY_SCALE_TABLE SSD1322_CMD_SET_GRAY_SCALE_TABLE
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#define SSD1353_CMD_SET_DEFAULT_GRAY_SCALE_TABLE SSD1322_CMD_SET_DEFAULT_GRAY_SCALE_TABLE
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#define SSD1353_CMD_SET_PRE_CHARGE_VOLTAGE_LEVEL SSD1322_CMD_SET_PRE_CHARGE_VOLTAGE_LEVEL
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#define SSD1353_DEFAULT_PRE_CHARGE_VOLTAGE_LEVEL 0x3e
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#define SSD1353_CMD_SET_VCOMH SSD1322_CMD_SET_VCOMH
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#define SSD1353_DEFAULT_VCOMH 0x3c
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#define SSD1353_CMD_OTP_WRITE 0xc0
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#define SSD1353_CMD_RESET 0xe2
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#define SSD1353_CMD_NOP SSDFB_CMD_NOP
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#define SSD1353_CMD_SET_COMMAND_LOCK SSD1322_CMD_SET_COMMAND_LOCK
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#define SSD1353_COMMAND_UNLOCK_MAGIC SSD1322_COMMAND_UNLOCK_MAGIC
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#define SSD1353_COMMAND_LOCK_MAGIC SSD1353_COMMAND_LOCK_MAGIC
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struct ssdfb_softc;
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typedef enum {
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SSDFB_CONTROLLER_UNKNOWN=0,
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SSDFB_CONTROLLER_SSD1306=1,
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SSDFB_CONTROLLER_SH1106=2,
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SSDFB_CONTROLLER_SSD1322=3,
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SSDFB_CONTROLLER_SSD1353=4,
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} ssdfb_controller_id_t;
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typedef enum {
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SSDFB_PRODUCT_UNKNOWN=0,
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SSDFB_PRODUCT_SSD1306_GENERIC=1,
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SSDFB_PRODUCT_SH1106_GENERIC=2,
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SSDFB_PRODUCT_ADAFRUIT_931=3,
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SSDFB_PRODUCT_ADAFRUIT_938=4,
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SSDFB_PRODUCT_SSD1322_GENERIC=5,
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SSDFB_PRODUCT_SSD1353_GENERIC=6,
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SSDFB_PRODUCT_DEP_160128A_RGB=7,
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} ssdfb_product_id_t;
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#define SSDFB_I2C_DEFAULT_ADDR 0x3c
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#define SSDFB_I2C_ALTERNATIVE_ADDR 0x3d
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/* Co bit has different behaviour in SSD1306 and SH1106 */
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#define SSDFB_I2C_CTRL_BYTE_CONTINUATION_MASK __BIT(7)
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#define SSDFB_I2C_CTRL_BYTE_DATA_MASK __BIT(6)
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union ssdfb_block {
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uint8_t col[8];
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uint64_t raw;
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};
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struct ssdfb_product {
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ssdfb_product_id_t p_product_id;
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ssdfb_controller_id_t p_controller_id;
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const char *p_name;
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int p_width;
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int p_height;
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int p_bits_per_pixel;
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bool p_rgb;
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int p_panel_shift;
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uint8_t p_fosc;
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uint8_t p_fosc_div;
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uint8_t p_precharge;
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uint8_t p_discharge;
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uint8_t p_compin_cfg;
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uint8_t p_vcomh_deselect_level;
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uint8_t p_default_contrast;
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uint8_t p_multiplex_ratio;
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int (*p_init)(struct ssdfb_softc *);
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int (*p_sync)(struct ssdfb_softc *, bool);
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};
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struct ssdfb_softc {
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device_t sc_dev;
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const struct ssdfb_product *sc_p;
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/* wscons & rasops state */
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u_int sc_mode;
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int sc_fontcookie;
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struct wsdisplay_font *sc_font;
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struct wsscreen_descr sc_screen_descr;
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const struct wsscreen_descr *sc_screens[1];
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struct wsscreen_list sc_screenlist;
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struct rasops_info sc_ri;
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size_t sc_ri_bits_len;
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struct wsdisplay_emulops sc_orig_riops;
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int sc_nscreens;
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device_t sc_wsdisplay;
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bool sc_is_console;
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bool sc_usepoll;
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/* hardware state */
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bool sc_upsidedown;
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bool sc_inverse;
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uint8_t sc_contrast;
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bool sc_display_on;
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union ssdfb_block *sc_gddram;
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size_t sc_gddram_len;
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/* damage tracking */
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lwp_t *sc_thread;
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kcondvar_t sc_cond;
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kmutex_t sc_cond_mtx;
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bool sc_detaching;
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int sc_backoff;
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bool sc_modified;
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struct uvm_object *sc_uobj;
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/* reference to bus-specific code */
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void *sc_cookie;
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int (*sc_cmd)(void *, uint8_t *, size_t, bool);
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int (*sc_transfer_rect)(void *, uint8_t, uint8_t, uint8_t, uint8_t,
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uint8_t *, size_t, bool);
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};
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void ssdfb_attach(struct ssdfb_softc *, int flags);
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int ssdfb_detach(struct ssdfb_softc *);
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