292 lines
7.2 KiB
C
292 lines
7.2 KiB
C
/* $NetBSD: s3c2800_clk.c,v 1.16 2011/07/01 20:31:39 dyoung Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2800_clk.c,v 1.16 2011/07/01 20:31:39 dyoung Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/atomic.h>
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#include <sys/time.h>
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#include <sys/timetc.h>
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#include <sys/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <arm/s3c2xx0/s3c2800reg.h>
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#include <arm/s3c2xx0/s3c2800var.h>
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#ifndef STATHZ
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#define STATHZ 64
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#endif
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#define TIMER_FREQUENCY(pclk) ((pclk)/32) /* divider=1/32 */
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static unsigned int timer0_reload_value;
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static unsigned int timer0_prescaler;
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static unsigned int timer0_mseccount;
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#define usec_to_counter(t) \
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((timer0_mseccount*(t))/1000)
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#define counter_to_usec(c,pclk) \
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(((c)*timer0_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000))
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static u_int s3c2800_get_timecount(struct timecounter *);
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static struct timecounter s3c2800_timecounter = {
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s3c2800_get_timecount, /* get_timecount */
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0, /* no poll_pps */
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0xffffffff, /* counter_mask */
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0, /* frequency */
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"s3c23800", /* name */
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100, /* quality */
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NULL, /* prev */
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NULL, /* next */
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};
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static volatile uint32_t s3c2800_base;
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static u_int
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s3c2800_get_timecount(struct timecounter *tc)
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{
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struct s3c2800_softc *sc = (struct s3c2800_softc *) s3c2xx0_softc;
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int save, int_pend0, int_pend1, count;
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save = disable_interrupts(I32_bit);
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again:
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int_pend0 = S3C2800_INT_TIMER0 &
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bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh,
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INTCTL_SRCPND);
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count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh,
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TIMER_TMCNT);
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for (;;){
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int_pend1 = S3C2800_INT_TIMER0 &
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bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh,
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INTCTL_SRCPND);
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if( int_pend0 == int_pend1 )
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break;
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/*
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* Down counter reached to zero while we were reading
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* timer values. do it again to get consistent values.
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*/
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int_pend0 = int_pend1;
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count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh,
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TIMER_TMCNT);
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}
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if( __predict_false(count > timer0_reload_value) ){
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/*
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* Buggy Hardware Warning --- sometimes timer counter
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* reads bogus value like 0xffff. I guess it happens when
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* the timer is reloaded.
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*/
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#if 0
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printf( "Bogus value from timer counter: %d\n", count );
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#endif
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goto again;
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}
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restore_interrupts(save);
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if (int_pend1)
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count -= timer0_reload_value;
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return s3c2800_base - count;
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}
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static inline int
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read_timer(struct s3c2800_softc *sc)
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{
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int count;
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do {
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count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh,
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TIMER_TMCNT);
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} while ( __predict_false(count > timer0_reload_value) );
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return count;
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}
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/*
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* delay:
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*
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* Delay for at least N microseconds.
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*/
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void
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delay(u_int n)
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{
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struct s3c2800_softc *sc = (struct s3c2800_softc *) s3c2xx0_softc;
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int v0, v1, delta;
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u_int ucnt;
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if ( timer0_reload_value == 0 ){
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/* not initialized yet */
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while ( n-- > 0 ){
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int m;
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for (m=0; m<100; ++m )
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;
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}
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return;
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}
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/* read down counter */
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v0 = read_timer(sc);
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ucnt = usec_to_counter(n);
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while( ucnt > 0 ) {
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v1 = read_timer(sc);
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delta = v0 - v1;
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if ( delta < 0 )
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delta += timer0_reload_value;
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#ifdef DEBUG
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if (delta < 0 || delta > timer0_reload_value)
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panic("wrong value from timer counter");
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#endif
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if((u_int)delta < ucnt){
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ucnt -= (u_int)delta;
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v0 = v1;
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}
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else {
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ucnt = 0;
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}
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}
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/*NOTREACHED*/
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}
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void
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setstatclockrate(int newhz)
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{
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}
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static int
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hardintr(void *arg)
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{
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atomic_add_32(&s3c2800_base, timer0_reload_value);
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hardclock((struct clockframe *)arg);
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return 1;
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}
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static int
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statintr(void *arg)
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{
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statclock((struct clockframe *)arg);
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return 1;
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}
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void
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cpu_initclocks(void)
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{
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struct s3c2800_softc *sc = (struct s3c2800_softc *)s3c2xx0_softc;
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long tc;
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int prescaler;
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int pclk = s3c2xx0_softc->sc_pclk;
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stathz = STATHZ;
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profhz = stathz;
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#define calc_time_constant(hz) \
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do { \
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prescaler = 1; \
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do { \
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++prescaler; \
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tc = TIMER_FREQUENCY(pclk) /(hz)/ prescaler; \
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} while( tc > 65536 ); \
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} while(0)
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/* Use the channels 0 and 1 for hardclock and statclock, respectively */
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bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMCON, 0);
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bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMCON, 0);
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calc_time_constant(hz);
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bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMDAT,
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((prescaler - 1) << 16) | (tc - 1));
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timer0_prescaler = prescaler;
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timer0_reload_value = tc;
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timer0_mseccount = TIMER_FREQUENCY(pclk)/timer0_prescaler/1000 ;
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printf("clock: hz=%d stathz = %d PCLK=%d prescaler=%d tc=%ld\n",
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hz, stathz, pclk, prescaler, tc);
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calc_time_constant(stathz);
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bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMDAT,
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((prescaler - 1) << 16) | (tc - 1));
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s3c2800_intr_establish(S3C2800_INT_TIMER0, IPL_CLOCK,
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IST_NONE, hardintr, 0);
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s3c2800_intr_establish(S3C2800_INT_TIMER1, IPL_HIGH,
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IST_NONE, statintr, 0);
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/* start timers */
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bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMCON,
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TMCON_MUX_DIV32|TMCON_INTENA|TMCON_ENABLE);
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bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMCON,
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TMCON_MUX_DIV4|TMCON_INTENA|TMCON_ENABLE);
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/* stop timer2 */
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{
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bus_space_handle_t tmp_ioh;
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bus_space_map(sc->sc_sx.sc_iot, S3C2800_TIMER2_BASE,
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S3C2800_TIMER_SIZE, 0, &tmp_ioh);
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bus_space_write_4(sc->sc_sx.sc_iot, tmp_ioh,
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TIMER_TMCON, 0);
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bus_space_unmap(sc->sc_sx.sc_iot, tmp_ioh,
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S3C2800_TIMER_SIZE);
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}
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s3c2800_timecounter.tc_frequency = TIMER_FREQUENCY(pclk) / timer0_prescaler;
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tc_init(&s3c2800_timecounter);
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}
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