159 lines
5.5 KiB
C
159 lines
5.5 KiB
C
/* $NetBSD: cache_sh3.h,v 1.8 2006/03/04 01:55:03 uwe Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* SH3: SH7708, SH7708S, SH7708R, SH7709, SH7709A
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*/
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#ifndef _SH3_CACHE_SH3_H_
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#define _SH3_CACHE_SH3_H_
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#include <sh3/devreg.h>
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#ifdef _KERNEL
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#define SH3_CCR 0xffffffec
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#define SH3_CCR_CE 0x00000001
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#define SH3_CCR_WT 0x00000002
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/* SH7708 don't have CB bit */
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#define SH3_CCR_CB 0x00000004
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#define SH3_CCR_CF 0x00000008
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/* SH7709A don't have RA bit */
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#define SH3_CCR_RA 0x00000020
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/* SH7709A specific cache-lock control register */
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#define SH7709A_CCR2 0xa40000b0
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#define SH7709A_CCR2_W2LOCK 0x00000001
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#define SH7709A_CCR2_W2LOAD 0x00000002
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#define SH7709A_CCR2_W3LOCK 0x00000100
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#define SH7709A_CCR2_W3LOAD 0x00000200
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#define SH3_CCA 0xf0000000
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/* Address specification */
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#define CCA_A 0x00000008
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#define CCA_ENTRY_SHIFT 4
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/* 8KB cache (SH7708, SH7708S, SH7708R, SH7709) */
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#define CCA_8K_ENTRY 128
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#define CCA_8K_ENTRY_MASK 0x000007f0 /* [10:4] */
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#define CCA_8K_WAY_SHIFT 11
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#define CCA_8K_WAY_MASK 0x00001800 /* [12:11] */
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/* 16KB cache (SH7709A) */
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#define CCA_16K_ENTRY 256
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#define CCA_16K_ENTRY_MASK 0x00000ff0 /* [11:4] */
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#define CCA_16K_WAY_SHIFT 12
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#define CCA_16K_WAY_MASK 0x00003000 /* [13:12] */
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/* Data specification */
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#define CCA_V 0x00000001
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#define CCA_U 0x00000002
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#define CCA_LRU_SHIFT 4
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#define CCA_LRU_MASK 0x000003f0 /* [9:4] */
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#define CCA_TAGADDR_SHIFT 10
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#define CCA_TAGADDR_MASK 0xfffffc00 /* [31:10] */
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#define SH3_CCD 0xf1000000
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/* Address specification */
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#define CCD_L_SHIFT 2
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#define CCD_L_MASK 0x0000000c /* [3:2] */
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#define CCD_E_SHIFT 4
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#define CCD_8K_E_MASK 0x000007f0 /* [10:4] */
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#define CCD_16K_E_MASK 0x00000ff0 /* [11:4] */
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#define CCD_8K_W_SHIFT 11
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#define CCD_8K_W_MASK 0x00001800 /* [12:11] */
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#define CCD_16K_W_SHIFT 12
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#define CCD_16K_W_MASK 0x00003000 /* [13:12] */
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/* Data specification */
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/*
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* Configuration
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*/
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#define SH3_CACHE_LINESZ 16
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#define SH3_CACHE_NORMAL_WAY 4
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#define SH3_CACHE_RAMMODE_WAY 2
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#define SH3_CACHE_8K_ENTRY 128
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#define SH3_CACHE_8K_WAY_NORMAL 4
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#define SH3_CACHE_8K_WAY_RAMMODE 2
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#define SH3_CACHE_16K_ENTRY 256
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#define SH3_CACHE_16K_WAY 4
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/*
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* cache flush macro for locore level code.
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*/
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#define SH3_CACHE_8K_FLUSH(maxway) \
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do { \
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uint32_t __e, __w, __wa, __a; \
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\
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for (__w = 0; __w < maxway; __w++) { \
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__wa = SH3_CCA | __w << CCA_8K_WAY_SHIFT; \
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for (__e = 0; __e < CCA_8K_ENTRY; __e++) { \
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__a = __wa |(__e << CCA_ENTRY_SHIFT); \
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(*(volatile uint32_t *)__a) &= \
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~(CCA_U | CCA_V); \
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} \
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} \
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} while (/*CONSTCOND*/0)
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#define SH3_CACHE_16K_FLUSH() \
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do { \
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uint32_t __e, __w, __wa, __a; \
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\
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for (__w = 0; __w < SH3_CACHE_16K_WAY; __w++) { \
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__wa = SH3_CCA | __w << CCA_16K_WAY_SHIFT; \
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for (__e = 0; __e < CCA_16K_ENTRY; __e++) { \
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__a = __wa |(__e << CCA_ENTRY_SHIFT); \
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(*(volatile uint32_t *)__a) &= \
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~(CCA_U | CCA_V); \
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} \
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} \
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} while (/*CONSTCOND*/0)
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#define SH7708_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4)
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#define SH7708_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2)
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#define SH7708S_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4)
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#define SH7708S_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2)
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#define SH7708R_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4)
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#define SH7708R_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2)
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#define SH7709_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4)
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#define SH7709_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2)
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#define SH7709A_CACHE_FLUSH() SH3_CACHE_16K_FLUSH()
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#ifndef _LOCORE
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extern void sh3_cache_config(void);
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#endif
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#endif /* _KERNEL */
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#endif /* !_SH3_CACHE_SH3_H_ */
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