80 lines
2.8 KiB
C
80 lines
2.8 KiB
C
/* $NetBSD: armreg.h,v 1.1 2000/05/09 21:55:58 bjh21 Exp $ */
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/*-
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* Copyright (c) 1998 Ben Harris
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* This file is part of NetBSD/arm26 -- a port of NetBSD to ARM2/3 machines. */
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#ifndef _ARM26_ARMREG_H
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#define _ARM26_ARMREG_H
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/* All the junk the old ARMs stuff in R15 */
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#define R15_MODE 0x00000003
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#define R15_MODE_USR 0x00000000
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#define R15_MODE_FIQ 0x00000001
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#define R15_MODE_IRQ 0x00000002
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#define R15_MODE_SVC 0x00000003
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#define R15_PC 0x03fffffc
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#define R15_FIQ_DISABLE 0x04000000
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#define R15_IRQ_DISABLE 0x08000000
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#define R15_FLAGS 0xf0000000
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#define R15_FLAG_N 0x80000000
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#define R15_FLAG_Z 0x40000000
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#define R15_FLAG_C 0x20000000
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#define R15_FLAG_V 0x10000000
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#define ARM_CP15_CPU_ID 0
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/* Not really many CPUs to consider */
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#define CPU_ID_DESIGNER_MASK 0xff000000
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#define CPU_ID_ARM_LTD 0x41000000
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#define CPU_ID_TYPE_MASK 0x00ff0000
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#define CPU_ID_ARM 0x00560000
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#define CPU_ID_CPU_MASK 0x0000fff0
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#define CPU_ID_ARM3 0x00000300
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#define CPU_ID_REVISION_MASK 0x0000000f
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/* Fake CPU IDs for older ARMs */
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#define CPU_ID_ARM2 0x00000200
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#define CPU_ID_ARM250 0x00000250
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/* ARM3-specific coprocessor 15 register */
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#define ARM3_CP15_FLUSH 1
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#define ARM3_CP15_CONTROL 2
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#define ARM3_CP15_CACHEABLE 3
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#define ARM3_CP15_UPDATEABLE 4
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#define ARM3_CP15_DISRUPTIVE 5
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/* Control register bits */
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#define ARM3_CTL_CACHE_ON 1
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#define ARM3_CTL_SHARED 2
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#define ARM3_CTL_MONITOR 4
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#endif
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