d599df9587
add rd, pc, #foo - . - 8 -> adr rd, foo ldr rd, [pc, #foo - . - 8] -> ldr rd, foo Also, when saving the return address for a function pointer call, use "mov lr, pc" just before the call unless the return address is somewhere other than just after the call site. Finally, a few obvious little micro-optimisations like using LDR directly rather than ADR followed by LDR, and loading directly into PC rather than bouncing via R0.
151 lines
4.4 KiB
ArmAsm
151 lines
4.4 KiB
ArmAsm
/* $NetBSD: iq80321_start.S,v 1.4 2002/10/14 22:32:54 bjh21 Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#include <arm/arm32/pte.h>
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.section .start,"ax",%progbits
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.global _C_LABEL(iq80321_start)
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_C_LABEL(iq80321_start):
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/*
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* We will go ahead and disable the MMU here so that we don't
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* have to worry about flushing caches, etc.
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*
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* Note that we may not currently be running VA==PA, which means
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* we'll need to leap to the next insn after disabing the MMU.
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*/
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adr r8, Lunmapped
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bic r8, r8, #0xff000000 /* clear upper 8 bits */
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orr r8, r8, #0xa0000000 /* OR in physical base address */
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mrc p15, 0, r2, c1, c0, 0
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bic r2, r2, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r2, c1, c0, 0
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nop
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nop
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nop
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mov pc, r8 /* Heave-ho! */
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Lunmapped:
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/*
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* We want to construct a memory map that maps us
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* VA==PA (SDRAM at 0xa0000000) and also double-maps
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* that space at 0xc0000000 (where the kernel address
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* space starts). We create these mappings uncached
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* and unbuffered to be safe.
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*
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* We also want to map the various devices we want to
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* talk to VA==PA during bootstrap.
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*
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* We just use section mappings for all of this to make it easy.
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*
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* We will put the L1 table to do all this at 0xa0004000, which
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* is also where RedBoot puts it.
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*/
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/*
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* Step 1: Map the entire address space VA==PA.
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*/
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adr r0, Ltable
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ldr r0, [r0] /* r0 = &l1table */
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mov r3, #(L1_S_AP(AP_KRW))
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orr r3, r3, #(L1_TYPE_S)
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mov r2, #0x100000 /* advance by 1MB */
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mov r1, #0x1000 /* 4096MB */
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1:
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str r3, [r0], #0x04
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add r3, r3, r2
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subs r1, r1, #1
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bgt 1b
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/*
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* Step 2: Map VA 0xc0000000->0xc3ffffff to PA 0xa0000000->0xa3ffffff.
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*/
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adr r0, Ltable /* r0 = &l1table */
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ldr r0, [r0]
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mov r3, #(L1_S_AP(AP_KRW))
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orr r3, r3, #(L1_TYPE_S)
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orr r3, r3, #0xa0000000
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add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */
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mov r1, #0x40 /* 64MB */
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1:
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str r3, [r0], #0x04
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add r3, r3, r2
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subs r1, r1, #1
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bgt 1b
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/* OK! Page table is set up. Give it to the CPU. */
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adr r0, Ltable
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ldr r0, [r0]
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mcr p15, 0, r0, c2, c0, 0
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/* Flush the old TLBs, just in case. */
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mcr p15, 0, r0, c8, c7, 0
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/* Set the Domain Access register. Very important! */
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mov r0, #1
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mcr p15, 0, r0, c3, c0, 0
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/* Get ready to jump to the "real" kernel entry point... */
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ldr r0, Lstart
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/* OK, let's enable the MMU. */
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mrc p15, 0, r2, c1, c0, 0
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orr r2, r2, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r2, c1, c0, 0
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nop
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nop
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nop
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/* CPWAIT sequence to make sure the MMU is on... */
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mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
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mov r2, r2 /* force it to complete */
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mov pc, r0 /* leap to kernel entry point! */
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Ltable:
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.word 0xa0004000
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Lstart:
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.word start
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