735 lines
31 KiB
C
735 lines
31 KiB
C
/* $NetBSD: if_sipreg.h,v 1.7 2001/05/18 02:03:54 thorpej Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1999 Network Computer, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Network Computer, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_IF_SIPREG_H_
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#define _DEV_PCI_IF_SIPREG_H_
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/*
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* Register description for the Silicon Integrated Systems SiS 900,
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* SiS 7016, National Semiconductor DP83815 10/100, and National
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* Semiconduction DP83820 10/100/1000 PCI Ethernet controller.
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*
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* Written by Jason R. Thorpe for Network Computer, Inc.
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*/
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/*
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* Transmit FIFO size. Used to compute the transmit drain threshold.
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*
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* The transmit FIFO is arranged as a 512 32-bit memory array.
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*/
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#define SIP_TXFIFO_SIZE (512 * 4)
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/*
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* The SiS900 uses a single descriptor format for both transmit
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* and receive descriptor chains.
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*
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* Note the DP83820 can use 64-bit DMA addresses for link and bufptr.
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* However, we do not yet support that.
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*
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* For transmit, buffers need not be aligned. For receive, buffers
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* must be aligned to 4-byte (8-byte on DP83820) boundaries.
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*/
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struct sip_desc {
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#ifdef DP83820
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u_int32_t sipd_link; /* link to next descriptor */
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u_int32_t sipd_bufptr; /* pointer to DMA segment */
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u_int32_t sipd_cmdsts; /* command/status word */
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u_int32_t sipd_extsts; /* extended status */
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#else
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u_int32_t sipd_link; /* link to next descriptor */
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u_int32_t sipd_cmdsts; /* command/status word */
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u_int32_t sipd_bufptr; /* pointer to DMA segment */
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#endif /* DP83820 */
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};
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/*
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* CMDSTS bits common to transmit and receive.
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*/
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#define CMDSTS_OWN 0x80000000 /* owned by consumer */
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#define CMDSTS_MORE 0x40000000 /* more descriptors */
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#define CMDSTS_INTR 0x20000000 /* interrupt when ownership changes */
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#define CMDSTS_SUPCRC 0x10000000 /* suppress CRC */
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#define CMDSTS_OK 0x08000000 /* packet ok */
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#ifdef DP83820
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#define CMDSTS_SIZE_MASK 0x0000ffff /* packet size */
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#else
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#define CMDSTS_SIZE_MASK 0x000007ff /* packet size */
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#endif /* DP83820 */
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#define CMDSTS_SIZE(x) ((x) & CMDSTS_SIZE_MASK)
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/*
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* CMDSTS bits for transmit.
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*/
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#define CMDSTS_Tx_TXA 0x04000000 /* transmit abort */
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#define CMDSTS_Tx_TFU 0x02000000 /* transmit FIFO underrun */
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#define CMDSTS_Tx_CRS 0x01000000 /* carrier sense lost */
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#define CMDSTS_Tx_TD 0x00800000 /* transmit deferred */
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#define CMDSTS_Tx_ED 0x00400000 /* excessive deferral */
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#define CMDSTS_Tx_OWC 0x00200000 /* out of window collision */
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#define CMDSTS_Tx_EC 0x00100000 /* excessive collisions */
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#define CMDSTS_Tx_CCNT 0x000f0000 /* collision count */
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#define CMDSTS_COLLISIONS(x) (((x) & CMDSTS_Tx_CCNT) >> 16)
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/*
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* CMDSTS bits for receive.
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*/
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#define CMDSTS_Rx_RXA 0x04000000 /* receive abort */
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#define CMDSTS_Rx_RXO 0x02000000 /* receive overrun */
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#define CMDSTS_Rx_DEST 0x01800000 /* destination class */
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#define CMDSTS_Rx_LONG 0x00400000 /* packet too long */
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#define CMDSTS_Rx_RUNT 0x00200000 /* runt packet */
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#define CMDSTS_Rx_ISE 0x00100000 /* invalid symbol error */
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#define CMDSTS_Rx_CRCE 0x00080000 /* CRC error */
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#define CMDSTS_Rx_FAE 0x00040000 /* frame alignment error */
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#define CMDSTS_Rx_LBP 0x00020000 /* loopback packet */
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#ifdef DP83820
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#define CMDSTS_Rx_IRL 0x00010000 /* in-range length error */
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#else
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#define CMDSTS_Rx_COL 0x00010000 /* collision activity */
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#endif /* DP83820 */
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#define CMDSTS_Rx_DEST_REJ 0x00000000 /* packet rejected */
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#define CMDSTS_Rx_DEST_STA 0x00800000 /* matched station address */
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#define CMDSTS_Rx_DEST_MUL 0x01000000 /* multicast address */
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#define CMDSTS_Rx_DEST_BRD 0x01800000 /* broadcast address */
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#ifdef DP83820
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/*
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* EXTSTS bits.
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*/
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#define EXTSTS_Rx_UDPERR 0x00400000 /* UDP checksum error */
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#define EXTSTS_UDPPKT 0x00200000 /* perform UDP checksum */
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#define EXTSTS_Rx_TCPERR 0x00100000 /* TCP checksum error */
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#define EXTSTS_TCPPKT 0x00080000 /* perform TCP checksum */
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#define EXTSTS_Rx_IPERR 0x00040000 /* IP header checksum error */
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#define EXTSTS_IPPKT 0x00020000 /* perform IP header checksum */
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#define EXTSTS_VPKT 0x00010000 /* insert VLAN tag */
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#define EXTSTS_VTCI 0x0000ffff /* VLAN tag control information */
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#endif /* DP83820 */
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/*
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* PCI Configuration space registers.
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*/
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#define SIP_PCI_CFGIOA (PCI_MAPREG_START + 0x00)
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#define SIP_PCI_CFGMA (PCI_MAPREG_START + 0x04)
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#ifdef DP83820
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#define SIP_PCI_CFGMA1 (PCI_MAPREG_START + 0x08)
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#endif /* DP83820 */
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#define SIP_PCI_CFGEROMA 0x30 /* expansion ROM address */
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#define SIP_PCI_CFGPMC 0x40 /* power management cap. */
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#define SIP_PCI_CFGPMCSR 0x44 /* power management ctl. */
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/*
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* MAC Operation Registers
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*/
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#define SIP_CR 0x00 /* command register */
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#ifdef DP83820
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#define CR_RXPRI3 0x00010000 /* Rx priority queue select */
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#define CR_RXPRI2 0x00008000 /* Rx priority queue select */
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#define CR_RXPRI1 0x00004000 /* Rx priority queue select */
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#define CR_RXPRI0 0x00002000 /* Rx priority queue select */
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#define CR_TXPRI3 0x00001000 /* Tx priority queue select */
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#define CR_TXPRI2 0x00000800 /* Tx priority queue select */
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#define CR_TXPRI1 0x00000400 /* Tx priority queue select */
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#define CR_TXPRI0 0x00000200 /* Tx priority queue select */
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#endif /* DP83820 */
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#define CR_RST 0x00000100 /* software reset */
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#define CR_SWI 0x00000080 /* software interrupt */
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#define CR_RXR 0x00000020 /* receiver reset */
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#define CR_TXR 0x00000010 /* transmit reset */
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#define CR_RXD 0x00000008 /* receiver disable */
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#define CR_RXE 0x00000004 /* receiver enable */
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#define CR_TXD 0x00000002 /* transmit disable */
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#define CR_TXE 0x00000001 /* transmit enable */
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#define SIP_CFG 0x04 /* configuration register */
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#define CFG_LNKSTS 0x80000000 /* link status (83815) */
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#ifdef DP83820
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#define CFG_SPEED1000 0x40000000 /* 1000Mb/s input pin */
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#define CFG_SPEED100 0x20000000 /* 100Mb/s input pin */
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#define CFG_DUPSTS 0x10000000 /* full-duplex status */
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#define CFG_TBI_EN 0x01000000 /* ten-bit interface enable */
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#define CFG_MODE_1000 0x00400000 /* 1000Mb/s mode enable */
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#define CFG_PINT_DUP 0x00100000 /* interrupt on PHY DUP change */
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#define CFG_PINT_LNK 0x00080000 /* interrupt on PHY LNK change */
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#define CFG_PINT_SPD 0x00040000 /* interrupt on PHY SPD change */
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#define CFG_TMRTEST 0x00020000 /* timer test mode */
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#define CFG_MRM_DIS 0x00010000 /* MRM disable */
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#define CFG_MWI_DIS 0x00008000 /* MWI disable */
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#define CFG_T64ADDR 0x00004000 /* target 64-bit addressing enable */
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#define CFG_PCI64_DET 0x00002000 /* 64-bit PCI bus detected */
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#define CFG_DATA64_EN 0x00001000 /* 64-bit data enable */
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#define CFG_M64ADDR 0x00000800 /* master 64-bit addressing enable */
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#else
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#define CFG_SPEED100 0x40000000 /* 100Mb/s (83815) */
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#define CFG_FDUP 0x20000000 /* full duplex (83815) */
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#define CFG_POL 0x10000000 /* 10Mb/s polarity (83815) */
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#define CFG_ANEG_DN 0x08000000 /* autonegotiation done (83815) */
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#define CFG_PHY_CFG 0x00fc0000 /* PHY configuration (83815) */
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#define CFG_PINT_ACEN 0x00020000 /* PHY interrupt auto clear (83815) */
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#define CFG_PAUSE_ADV 0x00010000 /* pause advertise (83815) */
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#define CFG_ANEG_SEL 0x0000e000 /* autonegotiation select (83815) */
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#endif /* DP83820 */
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#define CFG_PHY_RST 0x00000400 /* PHY reset (83815) */
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#define CFG_PHY_DIS 0x00000200 /* PHY disable (83815) */
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#ifdef DP83820
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#define CFG_EXTSTS_EN 0x00000100 /* extended status enable */
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#else
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#define CFG_EUPHCOMP 0x00000100 /* 83810 descriptor compat (83815) */
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#endif /* DP83820 */
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#define CFG_REQALG 0x00000080 /* PCI bus request alg. */
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#define CFG_SB 0x00000040 /* single backoff */
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#define CFG_POW 0x00000020 /* program out of window timer */
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#define CFG_EXD 0x00000010 /* excessive defferal timer disable */
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#define CFG_PESEL 0x00000008 /* parity error detection action */
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#ifdef DP83820
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#define CFG_BROM_DIS 0x00000004 /* boot ROM disable */
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#define CFG_EXT_125 0x00000002 /* external 125MHz reference select */
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#endif /* DP83820 */
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#define CFG_BEM 0x00000001 /* big-endian mode */
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#define SIP_EROMAR 0x08 /* EEPROM access register */
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#ifdef DP83820
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#define EROMAR_MDC 0x00000040 /* MII clock */
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#define EROMAR_MDDIR 0x00000020 /* MII direction (1 == MAC->PHY) */
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#define EROMAR_MDIO 0x00000010 /* MII data */
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#endif /* DP83820 */
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#define EROMAR_EECS 0x00000008 /* chip select */
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#define EROMAR_EESK 0x00000004 /* clock */
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#define EROMAR_EEDO 0x00000002 /* data out */
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#define EROMAR_EEDI 0x00000001 /* data in */
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#define SIP_PTSCR 0x0c /* PCI test control register */
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#ifdef DP83820
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#define PTSCR_RBIST_RST 0x00002000 /* SRAM BIST reset */
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#define PTSCR_RBIST_EN 0x00000400 /* SRAM BIST enable */
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#define PTSCR_RBIST_DONE 0x00000200 /* SRAM BIST done */
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#define PTSCR_RBIST_RX1FAIL 0x00000100 /* Rx status FIFO BIST fail */
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#define PTSCR_RBIST_RX0FAIL 0x00000080 /* Rx data FIFO BIST fail */
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#define PTSCR_RBIST_TX0FAIL 0x00000020 /* Tx data FIFO BIST fail */
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#define PTSCR_RBIST_HFFAIL 0x00000010 /* hash filter BIST fail */
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#define PTSCR_RBIST_RXFAIL 0x00000008 /* Rx filter BIST failed */
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#define PTSCR_EELOAD_EN 0x00000004 /* EEPROM load initiate */
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#define PTSCR_EEBIST_EN 0x00000002 /* EEPROM BIST enable */
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#define PTSCR_EEBIST_FAIL 0x00000001 /* EEPROM BIST failed */
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#else
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#define PTSCR_DIS_TEST 0x40000000 /* discard timer test mode */
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#define PTSCR_EROM_TACC 0x0f000000 /* boot rom access time */
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#define PTSCR_TRRAMADR 0x001ff000 /* TX/RX RAM address */
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#define PTSCR_BMTEN 0x00000200 /* bus master test enable */
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#define PTSCR_RRTMEN 0x00000080 /* receive RAM test mode enable */
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#define PTSCR_TRTMEN 0x00000040 /* transmit RAM test mode enable */
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#define PTSCR_SRTMEN 0x00000020 /* status RAM test mode enable */
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#define PTSCR_SRAMADR 0x0000001f /* status RAM address */
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#endif /* DP83820 */
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#define SIP_ISR 0x10 /* interrupt status register */
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#ifdef DP83820
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#define ISR_TXDESC3 0x40000000 /* Tx queue 3 */
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#define ISR_TXDESC2 0x20000000 /* Tx queue 2 */
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#define ISR_TXDESC1 0x10000000 /* Tx queue 1 */
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#define ISR_TXDESC0 0x08000000 /* Tx queue 0 */
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#define ISR_RXDESC3 0x04000000 /* Rx queue 3 */
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#define ISR_RXDESC2 0x02000000 /* Rx queue 2 */
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#define ISR_RXDESC1 0x01000000 /* Rx queue 1 */
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#define ISR_RXDESC0 0x00800000 /* Rx queue 0 */
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#define ISR_TXRCMP 0x00400000 /* transmit reset complete */
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#define ISR_RXRCMP 0x00200000 /* receive reset complete */
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#define ISR_DPERR 0x00100000 /* detected parity error */
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#define ISR_SSERR 0x00080000 /* signalled system error */
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#define ISR_RMABT 0x00040000 /* received master abort */
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#define ISR_RTABT 0x00020000 /* received target abort */
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#else
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#define ISR_WAKEEVT 0x10000000 /* wake up event */
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#define ISR_PAUSE_END 0x08000000 /* end of transmission pause */
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#define ISR_PAUSE_ST 0x04000000 /* start of transmission pause */
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#define ISR_TXRCMP 0x02000000 /* transmit reset complete */
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#define ISR_RXRCMP 0x01000000 /* receive reset complete */
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#define ISR_DPERR 0x00800000 /* detected parity error */
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#define ISR_SSERR 0x00400000 /* signalled system error */
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#define ISR_RMABT 0x00200000 /* received master abort */
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#define ISR_RTABT 0x00100000 /* received target abort */
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#endif /* DP83820 */
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#define ISR_RXSOVR 0x00010000 /* Rx status FIFO overrun */
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#define ISR_HIBERR 0x00008000 /* high bits error set */
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#ifdef DP83820
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#define ISR_PHY 0x00004000 /* PHY interrupt */
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#define ISR_PME 0x00002000 /* power management event */
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#endif /* DP83820 */
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#define ISR_SWI 0x00001000 /* software interrupt */
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#ifdef DP83820
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#define ISR_MIB 0x00000800 /* MIB service */
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#endif /* DP83820 */
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#define ISR_TXURN 0x00000400 /* Tx underrun */
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#define ISR_TXIDLE 0x00000200 /* Tx idle */
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#define ISR_TXERR 0x00000100 /* Tx error */
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#define ISR_TXDESC 0x00000080 /* Tx descriptor interrupt */
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#define ISR_TXOK 0x00000040 /* Tx okay */
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#define ISR_RXORN 0x00000020 /* Rx overrun */
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#define ISR_RXIDLE 0x00000010 /* Rx idle */
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#define ISR_RXEARLY 0x00000008 /* Rx early */
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#define ISR_RXERR 0x00000004 /* Rx error */
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#define ISR_RXDESC 0x00000002 /* Rx descriptor interrupt */
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#define ISR_RXOK 0x00000001 /* Rx okay */
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#define SIP_IMR 0x14 /* interrupt mask register */
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/* See bits in SIP_ISR */
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#define SIP_IER 0x18 /* interrupt enable register */
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#define IER_IE 0x00000001 /* master interrupt enable */
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#ifdef DP83820
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#define SIP_IHR 0x1c /* interrupt hold-off register */
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#define IHR_IHCTL 0x00000100 /* interrupt hold-off control */
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#define IHR_IH 0x000000ff /* interrupt hold-off timer (100us) */
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#else
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#define SIP_ENPHY 0x1c /* enhanced PHY access register */
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#define ENPHY_PHYDATA 0xffff0000 /* PHY data */
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#define ENPHY_DATA_SHIFT 16
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#define ENPHY_PHYADDR 0x0000f800 /* PHY number (7016 only) */
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#define ENPHY_PHYADDR_SHIFT 11
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#define ENPHY_REGADDR 0x000007c0 /* PHY register */
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#define ENPHY_REGADDR_SHIFT 6
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#define ENPHY_RWCMD 0x00000020 /* 1 == read, 0 == write */
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#define ENPHY_ACCESS 0x00000010 /* PHY access enable */
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#endif /* DP83820 */
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#define SIP_TXDP 0x20 /* transmit descriptor pointer reg */
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#ifdef DP83820
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#define SIP_TXDP_HI 0x24 /* transmit descriptor pointer (high) reg */
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#endif /* DP83820 */
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#ifdef DP83820
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#define SIP_TXCFG 0x28 /* transmit configuration register */
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#else
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#define SIP_TXCFG 0x24 /* transmit configuration register */
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#endif /* DP83820 */
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#define TXCFG_CSI 0x80000000 /* carrier sense ignore */
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#define TXCFG_HBI 0x40000000 /* heartbeat ignore */
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#define TXCFG_MLB 0x20000000 /* MAC loopback */
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#define TXCFG_ATP 0x10000000 /* automatic transmit padding */
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#ifdef DP83820
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#define TXCFG_ECRETRY 0x008000000 /* excessive collision retry enable */
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#define TXCFG_MXDMA 0x00700000 /* max DMA burst size */
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#define TXCFG_MXDMA_1024 0x00000000 /* 1024 bytes */
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#define TXCFG_MXDMA_8 0x00100000 /* 8 bytes */
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#define TXCFG_MXDMA_16 0x00200000 /* 16 bytes */
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#define TXCFG_MXDMA_32 0x00300000 /* 32 bytes */
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#define TXCFG_MXDMA_64 0x00400000 /* 64 bytes */
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#define TXCFG_MXDMA_128 0x00500000 /* 128 bytes */
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#define TXCFG_MXDMA_256 0x00600000 /* 256 bytes */
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#define TXCFG_MXDMA_512 0x00700000 /* 512 bytes */
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#define TXCFG_BRST_DIS 0x00080000 /* 1000Mb/s burst disable */
|
|
#define TXCFG_FLTH 0x0000ff00 /* Fx fill threshold */
|
|
#define TXCFG_FLTH_SHIFT 8
|
|
#define TXCFG_DRTH 0x000000ff /* Tx drain threshold */
|
|
#else
|
|
#define TXCFG_MXDMA 0x00700000 /* max DMA burst size */
|
|
#define TXCFG_MXDMA_512 0x00000000 /* 512 bytes */
|
|
#define TXCFG_MXDMA_4 0x00100000 /* 4 bytes */
|
|
#define TXCFG_MXDMA_8 0x00200000 /* 8 bytes */
|
|
#define TXCFG_MXDMA_16 0x00300000 /* 16 bytes */
|
|
#define TXCFG_MXDMA_32 0x00400000 /* 32 bytes */
|
|
#define TXCFG_MXDMA_64 0x00500000 /* 64 bytes */
|
|
#define TXCFG_MXDMA_128 0x00600000 /* 128 bytes */
|
|
#define TXCFG_MXDMA_256 0x00700000 /* 256 bytes */
|
|
#define TXCFG_FLTH 0x00003f00 /* Tx fill threshold */
|
|
#define TXCFG_FLTH_SHIFT 8
|
|
#define TXCFG_DRTH 0x0000003f /* Tx drain threshold */
|
|
#endif /* DP83820 */
|
|
|
|
#ifdef DP83820
|
|
#define SIP_GPIOR 0x2c /* general purpose i/o register */
|
|
#define GPIOR_GP5_IN 0x00004000 /* GP 5 in */
|
|
#define GPIOR_GP4_IN 0x00002000 /* GP 4 in */
|
|
#define GPIOR_GP3_IN 0x00001000 /* GP 3 in */
|
|
#define GPIOR_GP2_IN 0x00000800 /* GP 2 in */
|
|
#define GPIOR_GP1_IN 0x00000400 /* GP 1 in */
|
|
#define GPIOR_GP5_OE 0x00000200 /* GP 5 out enable */
|
|
#define GPIOR_GP4_OE 0x00000100 /* GP 4 out enable */
|
|
#define GPIOR_GP3_OE 0x00000080 /* GP 3 out enable */
|
|
#define GPIOR_GP2_OE 0x00000040 /* GP 2 out enable */
|
|
#define GPIOR_GP1_OE 0x00000020 /* GP 1 out enable */
|
|
#define GPIOR_GP5_OUT 0x00000010 /* GP 5 out */
|
|
#define GPIOR_GP4_OUT 0x00000008 /* GP 4 out */
|
|
#define GPIOR_GP3_OUT 0x00000004 /* GP 3 out */
|
|
#define GPIOR_GP2_OUT 0x00000002 /* GP 2 out */
|
|
#define GPIOR_GP1_OUT 0x00000001 /* GP 1 out */
|
|
#endif /* DP83820 */
|
|
|
|
#define SIP_RXDP 0x30 /* receive descriptor pointer reg */
|
|
|
|
#ifdef DP83820
|
|
#define SIP_RXDP_HI 0x34 /* receive descriptor pointer (high) reg */
|
|
#endif /* DP83820 */
|
|
|
|
#ifdef DP83820
|
|
#define SIP_RXCFG 0x38 /* receive configuration register */
|
|
#else
|
|
#define SIP_RXCFG 0x34 /* receive configuration register */
|
|
#endif
|
|
#define RXCFG_AEP 0x80000000 /* accept error packets */
|
|
#define RXCFG_ARP 0x40000000 /* accept runt packets */
|
|
#ifdef DP83820
|
|
#define RXCFG_STRIPCRC 0x20000000 /* strip CRC */
|
|
#endif /* DP83820 */
|
|
#define RXCFG_ATX 0x10000000 /* accept transmit packets */
|
|
#define RXCFG_AJAB 0x08000000 /* accept jabber packets */
|
|
#ifdef DP83820
|
|
#define RXCFG_AIRL 0x04000000 /* accept in-range length err packets */
|
|
#define RXCFG_MXDMA 0x00700000 /* max DMA burst size */
|
|
#define RXCFG_MXDMA_1024 0x00000000 /* 1024 bytes */
|
|
#define RXCFG_MXDMA_8 0x00100000 /* 8 bytes */
|
|
#define RXCFG_MXDMA_16 0x00200000 /* 16 bytes */
|
|
#define RXCFG_MXDMA_32 0x00300000 /* 32 bytes */
|
|
#define RXCFG_MXDMA_64 0x00400000 /* 64 bytes */
|
|
#define RXCFG_MXDMA_128 0x00500000 /* 128 bytes */
|
|
#define RXCFG_MXDMA_256 0x00600000 /* 256 bytes */
|
|
#define RXCFG_MXDMA_512 0x00700000 /* 512 bytes */
|
|
#else
|
|
#define RXCFG_MXDMA 0x00700000 /* max DMA burst size */
|
|
#define RXCFG_MXDMA_512 0x00000000 /* 512 bytes */
|
|
#define RXCFG_MXDMA_4 0x00100000 /* 4 bytes */
|
|
#define RXCFG_MXDMA_8 0x00200000 /* 8 bytes */
|
|
#define RXCFG_MXDMA_16 0x00300000 /* 16 bytes */
|
|
#define RXCFG_MXDMA_32 0x00400000 /* 32 bytes */
|
|
#define RXCFG_MXDMA_64 0x00500000 /* 64 bytes */
|
|
#define RXCFG_MXDMA_128 0x00600000 /* 128 bytes */
|
|
#define RXCFG_MXDMA_256 0x00700000 /* 256 bytes */
|
|
#endif /* DP83820 */
|
|
#define RXCFG_DRTH 0x0000003e
|
|
#define RXCFG_DRTH_SHIFT 1
|
|
|
|
#ifdef DP83820
|
|
#define SIP_PQCR 0x3c /* priority queueing control register */
|
|
#define PQCR_RXPQ_4 0x0000000c /* 4 Rx queues */
|
|
#define PQCR_RXPQ_3 0x00000008 /* 3 Rx queues */
|
|
#define PQCR_RXPQ_2 0x00000004 /* 2 Rx queues */
|
|
#define PQCR_TXFAIR 0x00000002 /* Tx fairness enable */
|
|
#define PQCR_TXPQEN 0x00000001 /* Tx priority queueing enable */
|
|
#else
|
|
#define SIP_FLOWCTL 0x38 /* flow control register */
|
|
#define FLOWCTL_PAUSE 0x00000002 /* PAUSE flag */
|
|
#define FLOWCTL_FLOWEN 0x00000001 /* enable flow control */
|
|
|
|
#define SIP_NS_CCSR 0x3c /* CLKRUN control/status register (83815) */
|
|
#define CCSR_PMESTS 0x00008000 /* PME status */
|
|
#define CCSR_PMEEN 0x00000100 /* PME enable */
|
|
#define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */
|
|
#endif /* DP83820 */
|
|
|
|
#define SIP_NS_WCSR 0x40 /* WoL control/status register (83815) */
|
|
|
|
#define SIP_NS_PCR 0x44 /* pause control/status register (83815) */
|
|
|
|
#define SIP_RFCR 0x48 /* receive filter control register */
|
|
#define RFCR_RFEN 0x80000000 /* Rx filter enable */
|
|
#define RFCR_AAB 0x40000000 /* accept all broadcast */
|
|
#define RFCR_AAM 0x20000000 /* accept all multicast */
|
|
#define RFCR_AAP 0x10000000 /* accept all physical */
|
|
#define RFCR_APM 0x08000000 /* accept perfect match (83815) */
|
|
#define RFCR_APAT 0x07800000 /* accept pattern match (83815) */
|
|
#define RFCR_AARP 0x00400000 /* accept ARP (83815) */
|
|
#define RFCR_MHEN 0x00200000 /* multicast hash enable (83815) */
|
|
#define RFCR_UHEN 0x00100000 /* unicast hash enable (83815) */
|
|
#define RFCR_ULM 0x00080000 /* U/L bit mask (83815) */
|
|
#define RFCR_NS_RFADDR 0x000003ff /* Rx filter ext reg address (83815) */
|
|
#define RFCR_RFADDR 0x000f0000 /* Rx filter address */
|
|
#define RFCR_RFADDR_NODE0 0x00000000 /* node address 1, 0 */
|
|
#define RFCR_RFADDR_NODE2 0x00010000 /* node address 3, 2 */
|
|
#define RFCR_RFADDR_NODE4 0x00020000 /* node address 5, 4 */
|
|
#define RFCR_RFADDR_MC0 0x00040000 /* multicast hash word 0 */
|
|
#define RFCR_RFADDR_MC1 0x00050000 /* multicast hash word 1 */
|
|
#define RFCR_RFADDR_MC2 0x00060000 /* multicast hash word 2 */
|
|
#define RFCR_RFADDR_MC3 0x00070000 /* multicast hash word 3 */
|
|
#define RFCR_RFADDR_MC4 0x00080000 /* multicast hash word 4 */
|
|
#define RFCR_RFADDR_MC5 0x00090000 /* multicast hash word 5 */
|
|
#define RFCR_RFADDR_MC6 0x000a0000 /* multicast hash word 6 */
|
|
#define RFCR_RFADDR_MC7 0x000b0000 /* multicast hash word 7 */
|
|
|
|
#define RFCR_NS_RFADDR_PMATCH0 0x0000 /* perfect match octets 1-0 */
|
|
#define RFCR_NS_RFADDR_PMATCH2 0x0002 /* perfect match octets 3-2 */
|
|
#define RFCR_NS_RFADDR_PMATCH4 0x0004 /* perfect match octets 5-4 */
|
|
#define RFCR_NS_RFADDR_PCOUNT 0x0006 /* pattern count */
|
|
#ifdef DP83820
|
|
#define RFCR_NS_RFADDR_PCOUNT2 0x0008 /* pattern count 2, 3 */
|
|
#define RFCR_NS_RFADDR_SOPAS0 0x000a /* SecureOn 0, 1 */
|
|
#define RFCR_NS_RFADDR_SOPAS2 0x000c /* SecureOn 2, 3 */
|
|
#define RFCR_NS_RFADDR_SOPAS4 0x000e /* SecureOn 4, 5 */
|
|
#define RFCR_NS_RFADDR_FILTMEM 0x0100 /* hash memory */
|
|
#define RFCR_NS_RFADDR_PATMEM 0x0200 /* pattern memory */
|
|
#else
|
|
#define RFCR_NS_RFADDR_FILTMEM 0x0200 /* filter memory (hash/pattern) */
|
|
#endif /* DP83820 */
|
|
|
|
#define SIP_RFDR 0x4c /* receive filter data register */
|
|
#define RFDR_BMASK 0x00030000 /* byte mask (83815) */
|
|
#define RFDR_DATA 0x0000ffff /* data bits */
|
|
|
|
#define SIP_NS_BRAR 0x50 /* boot rom address (83815) */
|
|
#define BRAR_AUTOINC 0x80000000 /* autoincrement */
|
|
#define BRAR_ADDR 0x0000ffff /* address */
|
|
|
|
#define SIP_NS_BRDR 0x54 /* boot rom data (83815) */
|
|
|
|
#define SIP_NS_SRR 0x58 /* silicon revision register (83815) */
|
|
#ifdef DP83820
|
|
#define SRR_REV_B 0x00000103
|
|
#else
|
|
#define SRR_REV_A 0x00000101
|
|
#define SRR_REV_B_1 0x00000200
|
|
#define SRR_REV_B_2 0x00000201
|
|
#define SRR_REV_B_3 0x00000203
|
|
#define SRR_REV_C_1 0x00000300
|
|
#define SRR_REV_C_2 0x00000302
|
|
#endif /* DP83820 */
|
|
|
|
#define SIP_NS_MIBC 0x5c /* mib control register (83815) */
|
|
#define MIBC_MIBS 0x00000008 /* mib counter strobe */
|
|
#define MIBC_ACLR 0x00000004 /* clear all counters */
|
|
#define MIBC_FRZ 0x00000002 /* freeze all counters */
|
|
#define MIBC_WRN 0x00000001 /* warning test indicator */
|
|
|
|
#define SIP_NS_MIB(mibreg) /* mib data registers (83815) */ \
|
|
(0x60 + (mibreg))
|
|
#define MIB_RXErroredPkts 0x00
|
|
#define MIB_RXFCSErrors 0x04
|
|
#define MIB_RXMsdPktErrors 0x08
|
|
#define MIB_RXFAErrors 0x0c
|
|
#define MIB_RXSymbolErrors 0x10
|
|
#define MIB_RXFrameTooLong 0x14
|
|
#ifdef DP83820
|
|
#define MIB_RXIRLErrors 0x18
|
|
#define MIB_RXBadOpcodes 0x1c
|
|
#define MIB_RXPauseFrames 0x20
|
|
#define MIB_TXPauseFrames 0x24
|
|
#define MIB_TXSQEErrors 0x28
|
|
#else
|
|
#define MIB_RXTXSQEErrors 0x18
|
|
#endif /* DP83820 */
|
|
|
|
#ifndef DP83820
|
|
#define SIP_NS_PHY(miireg) /* PHY registers (83815) */ \
|
|
(0x80 + ((miireg) << 2))
|
|
#endif
|
|
|
|
#ifdef DP83820
|
|
#define SIP_TXDP1 0xa0 /* transmit descriptor pointer (pri 1) */
|
|
|
|
#define SIP_TXDP2 0xa4 /* transmit descriptor pointer (pri 2) */
|
|
|
|
#define SIP_TXDP3 0xa8 /* transmit descriptor pointer (pri 3) */
|
|
|
|
#define SIP_RXDP1 0xb0 /* receive descriptor pointer (pri 1) */
|
|
|
|
#define SIP_RXDP2 0xb4 /* receive descriptor pointer (pri 2) */
|
|
|
|
#define SIP_RXDP3 0xb8 /* receive descriptor pointer (pri 3) */
|
|
|
|
#define SIP_VRCR 0xbc /* VLAN/IP receive control register */
|
|
#define VRCR_RUDPE 0x00000080 /* reject UDP checksum errors */
|
|
#define VRCR_RTCPE 0x00000040 /* reject TCP checksum errors */
|
|
#define VRCR_RIPE 0x00000020 /* reject IP checksum errors */
|
|
#define VRCR_IPEN 0x00000010 /* IP checksum enable */
|
|
#define VRCR_DUTF 0x00000008 /* discard untagged frames */
|
|
#define VRCR_DVTF 0x00000004 /* discard VLAN tagged frames */
|
|
#define VRCR_VTREN 0x00000002 /* VLAN tag removal enable */
|
|
#define VRCR_VTDEN 0x00000001 /* VLAN tag detection enable */
|
|
|
|
#define SIP_VTCR 0xc0 /* VLAN/IP transmit control register */
|
|
#define VTCR_PPCHK 0x00000008 /* per-packet checksum generation */
|
|
#define VTCR_GCHK 0x00000004 /* global checksum generation */
|
|
#define VTCR_VPPTI 0x00000002 /* VLAN per-packet tag insertion */
|
|
#define VTCR_VGTI 0x00000001 /* VLAN global tag insertion */
|
|
|
|
#define SIP_VDR 0xc4 /* VLAN data register */
|
|
#define VDR_VTCI 0xffff0000 /* VLAN tag control information */
|
|
#define VDR_VTYPE 0x0000ffff /* VLAN type field */
|
|
|
|
#define SIP_NS_CCSR 0xcc /* CLKRUN control/status register (83815) */
|
|
#define CCSR_PMESTS 0x00008000 /* PME status */
|
|
#define CCSR_PMEEN 0x00000100 /* PME enable */
|
|
#define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */
|
|
|
|
#define SIP_TBICR 0xe0 /* TBI control register */
|
|
#define TBICR_MR_LOOPBACK 0x00004000 /* TBI PCS loopback enable */
|
|
#define TBICR_MR_AN_ENABLE 0x00001000 /* TBI autonegotiation enable */
|
|
#define TBICR_MR_RESTART_AN 0x00000200 /* restart TBI autoneogtiation */
|
|
|
|
#define SIP_TBISR 0xe4 /* TBI status register */
|
|
#define TBISR_MR_LINK_STATUS 0x00000020 /* TBI link status */
|
|
#define TBISR_MR_AN_COMPLETE 0x00000004 /* TBI autonegotiation complete */
|
|
|
|
#define SIP_TANAR 0xe8 /* TBI autoneg adv. register */
|
|
#define TANAR_NP 0x00008000 /* next page exchange required */
|
|
#define TANAR_RF2 0x00002000 /* remote fault 2 */
|
|
#define TANAR_RF1 0x00001000 /* remote fault 1 */
|
|
#define TANAR_PS2 0x00000100 /* pause encoding 2 */
|
|
#define TANAR_PS1 0x00000080 /* pause encoding 1 */
|
|
#define TANAR_HALF_DUP 0x00000040 /* adv. half duplex */
|
|
#define TANAR_FULL_DUP 0x00000020 /* adv. full duplex */
|
|
|
|
#define SIP_TANLPAR 0xec /* TBI autoneg link partner ability register */
|
|
/* See TANAR bits */
|
|
|
|
#define SIP_TANER 0xf0 /* TBI autoneg expansion register */
|
|
#define TANER_NPA 0x00000004 /* we support next page function */
|
|
#define TANER_PR 0x00000002 /* page received from link partner */
|
|
|
|
#define SIP_TESR 0xf4 /* TBI extended status register */
|
|
#define TESR_1000FDX 0x00008000 /* we support 1000base FDX */
|
|
#define TESR_1000HDX 0x00004000 /* we support 1000base HDX */
|
|
#else
|
|
#define SIP_PMCTL 0xb0 /* power management control register */
|
|
#define PMCTL_GATECLK 0x80000000 /* gate dual clock enable */
|
|
#define PMCTL_WAKEALL 0x40000000 /* wake on all Rx OK */
|
|
#define PMCTL_FRM3ACS 0x04000000 /* 3rd wake-up frame access */
|
|
#define PMCTL_FRM2ACS 0x02000000 /* 2nd wake-up frame access */
|
|
#define PMCTL_FRM1ACS 0x01000000 /* 1st wake-up frame access */
|
|
#define PMCTL_FRM3EN 0x00400000 /* 3rd wake-up frame match enable */
|
|
#define PMCTL_FRM2EN 0x00200000 /* 2nd wake-up frame match enable */
|
|
#define PMCTL_FRM1EN 0x00100000 /* 1st wake-up frame match enable */
|
|
#define PMCTL_ALGORITHM 0x00000800 /* Magic Packet match algorithm */
|
|
#define PMCTL_MAGICPKT 0x00000400 /* Magic Packet match enable */
|
|
#define PMCTL_LINKON 0x00000002 /* link on monitor enable */
|
|
#define PMCTL_LINKLOSS 0x00000001 /* link loss monitor enable */
|
|
|
|
#define SIP_PMEVT 0xb4 /* power management wake-up evnt reg */
|
|
#define PMEVT_ALLFRMMAT 0x40000000 /* receive packet ok */
|
|
#define PMEVT_FRM3MAT 0x04000000 /* match 3rd wake-up frame */
|
|
#define PMEVT_FRM2MAT 0x02000000 /* match 2nd wake-up frame */
|
|
#define PMEVT_FRM1MAT 0x01000000 /* match 1st wake-up frame */
|
|
#define PMEVT_MAGICPKT 0x00000400 /* Magic Packet */
|
|
#define PMEVT_ONEVT 0x00000002 /* link on event */
|
|
#define PMEVT_LOSSEVT 0x00000001 /* link loss event */
|
|
|
|
#define SIP_WAKECRC 0xbc /* wake-up frame CRC register */
|
|
|
|
#define SIP_WAKEMASK0 0xc0 /* wake-up frame mask registers */
|
|
#define SIP_WAKEMASK1 0xc4
|
|
#define SIP_WAKEMASK2 0xc8
|
|
#define SIP_WAKEMASK3 0xcc
|
|
#define SIP_WAKEMASK4 0xe0
|
|
#define SIP_WAKEMASK5 0xe4
|
|
#define SIP_WAKEMASK6 0xe8
|
|
#define SIP_WAKEMASK7 0xec
|
|
#endif /* DP83820 */
|
|
|
|
/*
|
|
* Serial EEPROM opcodes, including the start bit.
|
|
*/
|
|
#define SIP_EEPROM_OPC_ERASE 0x04
|
|
#define SIP_EEPROM_OPC_WRITE 0x05
|
|
#define SIP_EEPROM_OPC_READ 0x06
|
|
|
|
/*
|
|
* Serial EEPROM address map (byte address) for the SiS900.
|
|
*/
|
|
#define SIP_EEPROM_SIGNATURE 0x00 /* SiS 900 signature */
|
|
#define SIP_EEPROM_MASK 0x02 /* `enable' mask */
|
|
#define SIP_EEPROM_VENDOR_ID 0x04 /* PCI vendor ID */
|
|
#define SIP_EEPROM_DEVICE_ID 0x06 /* PCI device ID */
|
|
#define SIP_EEPROM_SUBVENDOR_ID 0x08 /* PCI subvendor ID */
|
|
#define SIP_EEPROM_SUBSYSTEM_ID 0x0a /* PCI subsystem ID */
|
|
#define SIP_EEPROM_PMC 0x0c /* PCI power management capabilities */
|
|
#define SIP_EEPROM_reserved 0x0e /* reserved */
|
|
#define SIP_EEPROM_ETHERNET_ID0 0x10 /* Ethernet address 0, 1 */
|
|
#define SIP_EEPROM_ETHERNET_ID1 0x12 /* Ethernet address 2, 3 */
|
|
#define SIP_EEPROM_ETHERNET_ID2 0x14 /* Ethernet address 4, 5 */
|
|
#define SIP_EEPROM_CHECKSUM 0x16 /* checksum */
|
|
|
|
/*
|
|
* Serial EEPROM data (byte addresses) for the DP83815.
|
|
*/
|
|
#define SIP_DP83815_EEPROM_CHECKSUM 0x16 /* checksum */
|
|
#define SIP_DP83815_EEPROM_LENGTH 0x18 /* length of EEPROM data */
|
|
|
|
/*
|
|
* Serial EEPROM data (byte addresses) for the DP83820.
|
|
*/
|
|
#define SIP_DP83820_EEPROM_SUBSYSTEM_ID 0x00 /* PCI subsystem ID */
|
|
#define SIP_DP83820_EEPROM_SUBVENDOR_ID 0x02 /* PCI subvendor ID */
|
|
#define SIP_DP83820_EEPROM_CFGINT 0x04 /* PCI INT [31:16] */
|
|
#define SIP_DP83820_EEPROM_SOPAS0 0x0e /* SecureOn [47:32] */
|
|
#define SIP_DP83820_EEPROM_SOPAS1 0x10 /* SecureOn [31:16] */
|
|
#define SIP_DP83820_EEPROM_SOPAS2 0x12 /* SecureOn [15:0] */
|
|
#define SIP_DP83820_EEPROM_PMATCH0 0x14 /* MAC [47:32] */
|
|
#define SIP_DP83820_EEPROM_PMATCH1 0x16 /* MAC [31:16] */
|
|
#define SIP_DP83820_EEPROM_PMATCH2 0x18 /* MAC [15:0] */
|
|
#define SIP_DP83820_EEPROM_CHECKSUM 0x1a /* checksum */
|
|
#define SIP_DP83820_EEPROM_LENGTH 0x1c /* length of EEPROM data */
|
|
|
|
#endif /* _DEV_PCI_IF_SIPREG_H_ */
|