bf2dcec4f5
and only splnet() is allowed for the protection of data structures used by network devices.
99 lines
3.8 KiB
C
99 lines
3.8 KiB
C
/* $NetBSD: intr.h,v 1.10 2001/04/13 23:29:59 thorpej Exp $ */
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/*
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* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define IPL_NONE 0 /* Disable only this interrupt. */
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#define IPL_BIO 1 /* Disable block I/O interrupts. */
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#define IPL_NET 2 /* Disable network interrupts. */
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#define IPL_TTY 3 /* Disable terminal interrupts. */
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#define IPL_IMP 4 /* Memory allocation */
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#define IPL_CLOCK 5 /* Disable clock interrupts. */
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#define IPL_STATCLOCK 6 /* Disable profiling interrupts. */
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#define IPL_HIGH 7 /* Disable all interrupts. */
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#define NIPL 8
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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/* Soft interrupt masks. */
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#define SIR_CLOCK 31
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#define SIR_NET 30
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#define SIR_CLOCKMASK ((1 << SIR_CLOCK))
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#define SIR_NETMASK ((1 << SIR_NET) | SIR_CLOCKMASK)
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#define SIR_ALLMASK (SIR_CLOCKMASK | SIR_NETMASK)
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#ifdef _KERNEL
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#ifndef _LOCORE
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#include <mips/cpuregs.h>
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extern int _splraise(int);
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extern int _spllower(int);
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extern int _splset(int);
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extern int _splget(void);
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extern void _splnone(void);
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extern void _setsoftintr(int);
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extern void _clrsoftintr(int);
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#define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0)
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#define setsoftnet() _setsoftintr(MIPS_SOFT_INT_MASK_1)
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#define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0)
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#define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1)
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#define splhigh() _splraise(MIPS_INT_MASK)
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#define spl0() (void)_spllower(0)
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#define splx(s) (void)_splset(s)
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#define SPLSOFT MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1
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#define SPLBIO SPLSOFT | MIPS_INT_MASK_4
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#define SPLNET SPLBIO | MIPS_INT_MASK_1 | MIPS_INT_MASK_2
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#define SPLTTY SPLNET | MIPS_INT_MASK_3
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#define SPLCLOCK SPLTTY | MIPS_INT_MASK_0 | MIPS_INT_MASK_5
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#define splbio() _splraise(SPLBIO)
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#define splnet() _splraise(SPLNET)
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#define spltty() _splraise(SPLTTY)
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#define splclock() _splraise(SPLCLOCK)
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#define splvm() splclock()
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#define splstatclock() splclock()
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#define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0)
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#define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
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#define splsched() splhigh()
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#define spllock() splhigh()
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extern unsigned int intrcnt[];
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#define SOFTCLOCK_INTR 0
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#define SOFTNET_INTR 1
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extern void * cpu_intr_establish(int, int, int (*)(void *), void *);
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extern void * icu_intr_establish(int, int, int, int (*)(void *), void *);
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#endif /* !_LOCORE */
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#endif /* _LOCORE */
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