586 lines
14 KiB
C
586 lines
14 KiB
C
/* $NetBSD: pcib.c,v 1.9 2001/06/22 06:02:55 thorpej Exp $ */
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: pcib.c,v 1.9 2001/06/22 06:02:55 thorpej Exp $");
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#include "opt_algor_p5064.h"
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#include "opt_algor_p6032.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/ic/i8259reg.h>
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#ifdef ALGOR_P5064
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#include <algor/algor/algor_p5064var.h>
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#endif
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#ifdef ALGOR_P6032
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#include <algor/algor/algor_p6032var.h>
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#endif
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const char *pcib_intrnames[16] = {
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"irq 0",
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"irq 1",
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"irq 2",
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"irq 3",
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"irq 4",
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"irq 5",
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"irq 6",
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"irq 7",
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"irq 8",
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"irq 9",
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"irq 10",
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"irq 11",
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"irq 12",
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"irq 13",
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"irq 14",
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"irq 15",
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};
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struct pcib_intrhead {
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LIST_HEAD(, algor_intrhand) intr_q;
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struct evcnt intr_count;
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int intr_type;
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};
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struct pcib_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh_icu1;
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bus_space_handle_t sc_ioh_icu2;
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bus_space_handle_t sc_ioh_elcr;
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struct algor_isa_chipset sc_ic;
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struct pcib_intrhead sc_intrtab[16];
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u_int16_t sc_imask;
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u_int16_t sc_elcr;
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#if defined(ALGOR_P5064)
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isa_chipset_tag_t sc_parent_ic;
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#endif
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u_int16_t sc_reserved;
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void *sc_ih;
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};
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int pcib_match(struct device *, struct cfdata *, void *);
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void pcib_attach(struct device *, struct device *, void *);
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struct cfattach pcib_ca = {
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sizeof(struct pcib_softc), pcib_match, pcib_attach,
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};
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int pcib_print(void *, const char *pnp);
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void pcib_isa_attach_hook(struct device *, struct device *,
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struct isabus_attach_args *);
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int pcib_intr(void *);
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void pcib_bridge_callback(struct device *);
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const struct evcnt *pcib_isa_intr_evcnt(void *, int);
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void *pcib_isa_intr_establish(void *, int, int, int,
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int (*)(void *), void *);
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void pcib_isa_intr_disestablish(void *, void *);
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int pcib_isa_intr_alloc(void *, int, int, int *);
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void pcib_set_icus(struct pcib_softc *);
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int
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pcib_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA)
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return (1);
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return (0);
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}
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void
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pcib_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pcib_softc *sc = (void *) self;
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struct pci_attach_args *pa = aux;
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char devinfo[256];
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int i;
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pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
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printf(": %s (rev. 0x%02x)\n", devinfo,
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PCI_REVISION(pa->pa_class));
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sc->sc_iot = pa->pa_iot;
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/*
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* Map the PIC/ELCR registers.
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*/
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if (bus_space_map(sc->sc_iot, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
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printf("%s: unable to map ELCR registers\n",
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sc->sc_dev.dv_xname);
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if (bus_space_map(sc->sc_iot, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
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printf("%s: unable to map ICU1 registers\n",
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sc->sc_dev.dv_xname);
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if (bus_space_map(sc->sc_iot, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
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printf("%s: unable to map ICU2 registers\n",
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sc->sc_dev.dv_xname);
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/* All interrupts default to "masked off". */
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sc->sc_imask = 0xffff;
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/* All interrupts default to edge-triggered. */
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sc->sc_elcr = 0;
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/*
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* Initialize the 8259s.
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*/
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/* reset, program device, 4 bytes */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_ICW1,
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ICW1_SELECT | ICW1_IC4);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_ICW2,
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ICW2_VECTOR(0)/*XXX*/);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_ICW3,
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ICW3_CASCADE(2));
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_ICW4,
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ICW4_8086);
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/* mask all interrupts */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW1,
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sc->sc_imask & 0xff);
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/* enable special mask mode */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW3,
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OCW3_SELECT | OCW3_SSMM | OCW3_SMM);
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/* read IRR by default */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW3,
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OCW3_SELECT | OCW3_RR);
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/* reset; program device, 4 bytes */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, PIC_ICW1,
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ICW1_SELECT | ICW1_IC4);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, PIC_ICW2,
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ICW2_VECTOR(0)/*XXX*/);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, PIC_ICW3,
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ICW3_SIC(2));
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, PIC_ICW4,
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ICW4_8086);
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/* mask all interrupts */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, PIC_OCW1,
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(sc->sc_imask >> 8) & 0xff);
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/* enable special mask mode */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, PIC_OCW3,
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OCW3_SELECT | OCW3_SSMM | OCW3_SMM);
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/* read IRR by default */
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, PIC_OCW3,
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OCW3_SELECT | OCW3_RR);
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/*
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* Default all interrupts to edge-triggered.
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*/
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_elcr, 0,
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sc->sc_elcr & 0xff);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_elcr, 1,
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(sc->sc_elcr >> 8) & 0xff);
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/*
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* Some ISA interrupts are reserved for devices that
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* we know are hard-wired to certain IRQs.
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*/
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sc->sc_reserved =
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(1U << 0) | /* timer */
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(1U << 1) | /* keyboard controller */
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(1U << 2) | /* PIC cascade */
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(1U << 3) | /* COM 2 */
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(1U << 4) | /* COM 1 */
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(1U << 6) | /* floppy */
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(1U << 7) | /* centronics */
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(1U << 8) | /* RTC */
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(1U << 12) | /* keyboard controller */
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(1U << 14) | /* IDE 0 */
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(1U << 15); /* IDE 1 */
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#if defined(ALGOR_P5064)
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/*
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* Some "ISA" interrupts are a little wacky, wired up directly
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* to the P-5064 interrupt controller.
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*/
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sc->sc_parent_ic = &p5064_configuration.ac_ic;
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#endif /* ALGOR_P5064 */
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/* Set up our ISA chipset. */
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sc->sc_ic.ic_v = sc;
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sc->sc_ic.ic_intr_evcnt = pcib_isa_intr_evcnt;
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sc->sc_ic.ic_intr_establish = pcib_isa_intr_establish;
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sc->sc_ic.ic_intr_disestablish = pcib_isa_intr_disestablish;
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sc->sc_ic.ic_intr_alloc = pcib_isa_intr_alloc;
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/* Initialize our interrupt table. */
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for (i = 0; i < 16; i++) {
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LIST_INIT(&sc->sc_intrtab[i].intr_q);
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evcnt_attach_dynamic(&sc->sc_intrtab[i].intr_count,
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EVCNT_TYPE_INTR, NULL, "pcib", pcib_intrnames[i]);
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sc->sc_intrtab[i].intr_type = IST_NONE;
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}
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/* Hook up our interrupt handler. */
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#if defined(ALGOR_P5064)
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sc->sc_ih = (*algor_intr_establish)(P5064_IRQ_ISABRIDGE,
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pcib_intr, sc);
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#elif defined(ALGOR_P6032)
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sc->sc_ih = (*algor_intr_establish)(P6032_IRQ_ISABRIDGE,
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pcib_intr, sc);
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#endif
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if (sc->sc_ih == NULL)
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printf("%s: WARNING: unable to register interrupt handler\n",
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sc->sc_dev.dv_xname);
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config_defer(self, pcib_bridge_callback);
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}
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void
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pcib_bridge_callback(self)
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struct device *self;
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{
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struct pcib_softc *sc = (struct pcib_softc *)self;
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struct isabus_attach_args iba;
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memset(&iba, 0, sizeof(iba));
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iba.iba_busname = "isa";
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#if defined(ALGOR_P5064)
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{
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struct p5064_config *acp = &p5064_configuration;
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iba.iba_iot = &acp->ac_iot;
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iba.iba_memt = &acp->ac_memt;
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iba.iba_dmat = &acp->ac_isa_dmat;
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}
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#elif defined(ALGOR_P6032)
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{
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struct p6032_config *acp = &p6032_configuration;
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iba.iba_iot = &acp->ac_iot;
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iba.iba_memt = &acp->ac_memt;
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iba.iba_dmat = &acp->ac_isa_dmat;
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}
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#endif
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iba.iba_ic = &sc->sc_ic;
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iba.iba_ic->ic_attach_hook = pcib_isa_attach_hook;
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(void) config_found(&sc->sc_dev, &iba, pcib_print);
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}
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int
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pcib_print(void *aux, const char *pnp)
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{
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struct isabus_attach_args *iba;
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if (pnp)
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printf("%s at %s", iba->iba_busname, pnp);
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return (UNCONF);
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}
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void
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pcib_isa_attach_hook(struct device *parent, struct device *self,
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struct isabus_attach_args *iba)
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{
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/* Nothing to do. */
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}
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void
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pcib_set_icus(struct pcib_softc *sc)
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{
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/* Enable the cascade IRQ (2) if 8-15 is enabled. */
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if ((sc->sc_imask & 0xff00) != 0xff00)
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sc->sc_imask &= ~(1U << 2);
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else
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sc->sc_imask |= (1U << 2);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW1,
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sc->sc_imask & 0xff);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, PIC_OCW1,
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(sc->sc_imask >> 8) & 0xff);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_elcr, 0,
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sc->sc_elcr & 0xff);
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_elcr, 1,
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(sc->sc_elcr >> 8) & 0xff);
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}
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int
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pcib_intr(void *v)
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{
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struct pcib_softc *sc = v;
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struct algor_intrhand *ih;
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int irq;
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for (;;) {
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW3,
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OCW3_SELECT | OCW3_POLL);
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irq = bus_space_read_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW3);
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if ((irq & OCW3_POLL_PENDING) == 0)
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return (1);
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irq = OCW3_POLL_IRQ(irq);
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if (irq == 2) {
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2,
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PIC_OCW3, OCW3_SELECT | OCW3_POLL);
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irq = bus_space_read_1(sc->sc_iot, sc->sc_ioh_icu2,
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PIC_OCW3);
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if (irq & OCW3_POLL_PENDING)
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irq = OCW3_POLL_IRQ(irq) + 8;
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else
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irq = 2;
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}
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sc->sc_intrtab[irq].intr_count.ev_count++;
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for (ih = LIST_FIRST(&sc->sc_intrtab[irq].intr_q);
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ih != NULL; ih = LIST_NEXT(ih, ih_q)) {
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(*ih->ih_func)(ih->ih_arg);
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}
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/* Send a specific EOI to the 8259. */
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if (irq > 7) {
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2,
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PIC_OCW2, OCW2_SELECT | OCW3_EOI | OCW3_SL |
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OCW2_ILS(irq & 7));
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irq = 2;
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}
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bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW2,
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OCW2_SELECT | OCW3_EOI | OCW3_SL | OCW2_ILS(irq));
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}
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}
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const struct evcnt *
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pcib_isa_intr_evcnt(void *v, int irq)
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{
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struct pcib_softc *sc = v;
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#if defined(ALGOR_P5064)
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if (p5064_isa_to_irqmap[irq] != -1)
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return (isa_intr_evcnt(sc->sc_parent_ic, irq));
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#endif
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return (&sc->sc_intrtab[irq].intr_count);
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}
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void *
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pcib_isa_intr_establish(void *v, int irq, int type, int level,
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int (*func)(void *), void *arg)
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{
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struct pcib_softc *sc = v;
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struct algor_intrhand *ih;
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int s;
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if (irq > 15 || irq == 2 || type == IST_NONE)
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panic("pcib_isa_intr_establish: bad irq or type");
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#if defined(ALGOR_P5064)
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if (p5064_isa_to_irqmap[irq] != -1)
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return (isa_intr_establish(sc->sc_parent_ic, irq, type,
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level, func, arg));
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#endif
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switch (sc->sc_intrtab[irq].intr_type) {
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case IST_NONE:
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sc->sc_intrtab[irq].intr_type = type;
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break;
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case IST_EDGE:
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case IST_LEVEL:
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if (type == sc->sc_intrtab[irq].intr_type)
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break;
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/* FALLTHROUGH */
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case IST_PULSE:
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/*
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* We can't share interrupts in this case.
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*/
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return (NULL);
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}
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ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
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if (ih == NULL)
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return (NULL);
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ih->ih_func = func;
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ih->ih_arg = arg;
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ih->ih_irq = irq;
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ih->ih_irqmap = NULL;
|
|
|
|
s = splhigh();
|
|
|
|
/* Insert the handler into the table. */
|
|
LIST_INSERT_HEAD(&sc->sc_intrtab[irq].intr_q, ih, ih_q);
|
|
sc->sc_intrtab[irq].intr_type = type;
|
|
|
|
/* Enable it, set trigger mode. */
|
|
sc->sc_imask &= ~(1 << irq);
|
|
if (sc->sc_intrtab[irq].intr_type == IST_LEVEL)
|
|
sc->sc_elcr |= (1 << irq);
|
|
else
|
|
sc->sc_elcr &= ~(1 << irq);
|
|
|
|
pcib_set_icus(sc);
|
|
|
|
splx(s);
|
|
|
|
return (ih);
|
|
}
|
|
|
|
void
|
|
pcib_isa_intr_disestablish(void *v, void *arg)
|
|
{
|
|
struct pcib_softc *sc = v;
|
|
struct algor_intrhand *ih = arg;
|
|
int s;
|
|
|
|
#if defined(ALGOR_P5064)
|
|
if (p5064_isa_to_irqmap[ih->ih_irq] != -1) {
|
|
isa_intr_disestablish(sc->sc_parent_ic, ih);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
s = splhigh();
|
|
|
|
LIST_REMOVE(ih, ih_q);
|
|
|
|
/* If there are no more handlers on this IRQ, disable it. */
|
|
if (LIST_FIRST(&sc->sc_intrtab[ih->ih_irq].intr_q) == NULL) {
|
|
sc->sc_imask |= (1 << ih->ih_irq);
|
|
pcib_set_icus(sc);
|
|
}
|
|
|
|
splx(s);
|
|
|
|
free(ih, M_DEVBUF);
|
|
}
|
|
|
|
int
|
|
pcib_isa_intr_alloc(void *v, int mask, int type, int *irq)
|
|
{
|
|
struct pcib_softc *sc = v;
|
|
int i, tmp, bestirq, count;
|
|
struct algor_intrhand *ih;
|
|
|
|
if (type == IST_NONE)
|
|
panic("pcib_intr_alloc: bogus type");
|
|
|
|
bestirq = -1;
|
|
count = -1;
|
|
|
|
mask &= ~sc->sc_reserved;
|
|
|
|
#if 0
|
|
printf("pcib_intr_alloc: mask = 0x%04x\n", mask);
|
|
#endif
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
if ((mask & (1 << i)) == 0)
|
|
continue;
|
|
|
|
switch (sc->sc_intrtab[i].intr_type) {
|
|
case IST_NONE:
|
|
/*
|
|
* If nothing's using the IRQ, just return it.
|
|
*/
|
|
*irq = i;
|
|
return (0);
|
|
|
|
case IST_EDGE:
|
|
case IST_LEVEL:
|
|
if (type != sc->sc_intrtab[i].intr_type)
|
|
continue;
|
|
/*
|
|
* If the IRQ is sharable, count the number of
|
|
* other handlers, and if it's smaller than the
|
|
* last IRQ like this, remember it.
|
|
*/
|
|
tmp = 0;
|
|
for (ih = LIST_FIRST(&sc->sc_intrtab[i].intr_q);
|
|
ih != NULL; ih = LIST_NEXT(ih, ih_q))
|
|
tmp++;
|
|
if (bestirq == -1 || count > tmp) {
|
|
bestirq = i;
|
|
count = tmp;
|
|
}
|
|
break;
|
|
|
|
case IST_PULSE:
|
|
/* This just isn't sharable. */
|
|
continue;
|
|
}
|
|
}
|
|
|
|
if (bestirq == -1)
|
|
return (1);
|
|
|
|
*irq = bestirq;
|
|
return (0);
|
|
}
|