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and pte_l2_s_cache_mode. The cache-meaningful bits are different for these descriptor types on some processor models. * Add pte_*_cache_mask, corresponding to each above, which has a mask of the cache-meangful bits, and define those for generic and XScale MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires use of the Extended Small Page L2 descriptor (the "X" bit overlaps with AP bits otherwise).