376 lines
9.1 KiB
C
376 lines
9.1 KiB
C
/* $NetBSD: cs89x0reg.h,v 1.6 1998/07/25 00:41:47 thorpej Exp $ */
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/*
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* Copyright 1997
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* Digital Equipment Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and conditions.
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* Subject to these conditions, you may download, copy, install,
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* use, modify and distribute this software in source and/or binary
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* form. No title or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions as
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* they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or logo of
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* Digital Equipment Corporation. Neither the "Digital Equipment
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* Corporation" name nor any trademark or logo of Digital Equipment
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* Corporation may be used to endorse or promote products derived
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* from this software without the prior written permission of
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* Digital Equipment Corporation.
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*
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* 3) This software is provided "AS-IS" and any express or implied
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* warranties, including but not limited to, any implied warranties
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* of merchantability, fitness for a particular purpose, or
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* non-infringement are disclaimed. In no event shall DIGITAL be
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* liable for any damages whatsoever, and in particular, DIGITAL
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* shall not be liable for special, indirect, consequential, or
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* incidental damages or damages for lost profits, loss of
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* revenue or loss of use, whether such damages arise in contract,
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* negligence, tort, under statute, in equity, at law or otherwise,
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* even if advised of the possibility of such damage.
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*/
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/*
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**++
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** FACILITY Crystal CS8900 Ethernet driver register description
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**
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** ABSTRACT
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**
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** This module provides CS8900 register definitions
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**
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** AUTHORS
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**
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** Peter Dettori SEA - Software Engineering.
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**
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** CREATION DATE:
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**
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** 13-Feb-1997.
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**
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** MODIFICATION HISTORY:
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**
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**--
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*/
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#ifndef _DEV_ISA_CS89X0REG_H_
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#define _DEV_ISA_CS89X0REG_H_
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/*
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* The CS8900 has 8 2-byte registers in I/O space.
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*/
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#define CS8900_IOSIZE 16
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/*
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* The CS8900 has a 4k memory space.
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*/
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#define CS8900_MEMSIZE 4096
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/*
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* Size of the DMA area used for packet reception.
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*/
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#if 0
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#define CS8900_DMASIZE (64*1024)
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#else
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#define CS8900_DMASIZE (16*1024)
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#endif
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/*
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* Validate various parameters.
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*/
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#define CS8900_MEMBASE_ISVALID(x) (((x) & (CS8900_MEMSIZE - 1)) == 0)
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#define CS8900_IRQ_ISVALID(x) ((x) == 5 || (x) == 10 || \
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(x) == 11 || (x) == 12)
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/* Chip Identification (PacketPage registers) */
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#define EISA_NUM_CRYSTAL 0x630E
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#define PROD_ID_MASK 0xE000
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#define PROD_ID_CS8900 0x0000
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#define PROD_ID_CS8920 0x4000
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#define PROD_ID_CS8920M 0x6000
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#define PROD_REV_MASK 0x1F00
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/* IO Port Offsets */
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#define PORT_RXTX_DATA 0x0000
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#define PORT_RXTX_DATA_1 0x0002
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#define PORT_TX_CMD 0x0004
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#define PORT_TX_LENGTH 0x0006
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#define PORT_ISQ 0x0008
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#define PORT_PKTPG_PTR 0x000A
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#define PORT_PKTPG_DATA 0x000C
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#define PORT_PKTPG_DATA_1 0x000E
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/* PacketPage Offsets */
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#define PKTPG_EISA_NUM 0x0000
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#define PKTPG_PRODUCT_ID 0x0002
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#define PKTPG_IO_BASE 0x0020
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#define PKTPG_INT_NUM 0x0022
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#define PKTPG_DMA_CHANNEL 0x0024
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#define PKTPG_DMA_START_FRAME 0x0026
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#define PKTPG_DMA_FRAME_COUNT 0x0028
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#define PKTPG_DMA_BYTE_COUNT 0x002A
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#define PKTPG_MEM_BASE 0x002C
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#define PKTPG_EEPROM_CMD 0x0040
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#define PKTPG_EEPROM_DATA 0x0042
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#define PKTPG_FRAME_BYTE_COUNT 0x0050
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#define PKTPG_RX_CFG 0x0102
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#define PKTPG_RX_CTL 0x0104
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#define PKTPG_TX_CFG 0x0106
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#define PKTPG_BUF_CFG 0x010A
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#define PKTPG_LINE_CTL 0x0112
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#define PKTPG_SELF_CTL 0x0114
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#define PKTPG_BUS_CTL 0x0116
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#define PKTPG_TEST_CTL 0x0118
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#define PKTPG_AUTONEG_CTL 0x011C
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#define PKTPG_ISQ 0x0120
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#define PKTPG_RX_EVENT 0x0124
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#define PKTPG_TX_EVENT 0x0128
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#define PKTPG_BUF_EVENT 0x012C
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#define PKTPG_RX_MISS 0x0130
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#define PKTPG_TX_COL 0x0132
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#define PKTPG_LINE_ST 0x0134
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#define PKTPG_SELF_ST 0x0136
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#define PKTPG_BUS_ST 0x0138
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#define PKTPG_TDR 0x013c
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#define PKTPG_AUTONEG_ST 0x013e
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#define PKTPG_TX_CMD 0x0144
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#define PKTPG_TX_LENGTH 0x0146
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#define PKTPG_LOG_ADDR 0x0150 /* logical address filter hash tbl */
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#define PKTPG_IND_ADDR 0x0158
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#define PKTPG_RX_STATUS 0x0400
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#define PKTPG_RX_LENGTH 0x0402
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#define PKTPG_RX_FRAME 0x0404
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#define PKTPG_TX_FRAME 0x0A00
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/* EEPROM Offsets */
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#define EEPROM_IND_ADDR_H 0x001C
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#define EEPROM_IND_ADDR_M 0x001D
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#define EEPROM_IND_ADDR_L 0x001E
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#define EEPROM_ISA_CFG 0x001F
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#define EEPROM_MEM_BASE 0x0020
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#define EEPROM_XMIT_CTL 0x0023
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#define EEPROM_ADPTR_CFG 0x0024
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/* Register Numbers */
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#define REG_NUM_MASK 0x003F
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#define REG_NUM_RX_EVENT 0x0004
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#define REG_NUM_TX_EVENT 0x0008
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#define REG_NUM_BUF_EVENT 0x000C
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#define REG_NUM_RX_MISS 0x0010
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#define REG_NUM_TX_COL 0x0012
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/* Self Control Register */
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#define SELF_CTL_RESET 0x0040
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#define SELF_CTL_HC1E 0x2000
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#define SELF_CTL_HCB1 0x8000
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/* Self Status Register */
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#define SELF_ST_INIT_DONE 0x0080
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#define SELF_ST_SI_BUSY 0x0100
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#define SELF_ST_EEP_PRES 0x0200
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#define SELF_ST_EEP_OK 0x0400
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#define SELF_ST_EL_PRES 0x0800
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/* EEPROM Command Register */
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#define EEPROM_CMD_READ 0x0200
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#define EEPROM_CMD_ELSEL 0x0400
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/* Bus Control Register */
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#define BUS_CTL_RESET_DMA 0x0040
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#define BUS_CTL_USE_SA 0x0200
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#define BUS_CTL_MEM_MODE 0x0400
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#define BUS_CTL_DMA_BURST 0x0800
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#define BUS_CTL_IOCHRDY 0x1000
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#define BUS_CTL_DMA_SIZE 0x2000
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#define BUS_CTL_INT_ENBL 0x8000
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/* Bus Status Register */
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#define BUS_ST_TX_BID_ERR 0x0080
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#define BUS_ST_RDY4TXNOW 0x0100
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/* Line Control Register */
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#define LINE_CTL_RX_ON 0x0040
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#define LINE_CTL_TX_ON 0x0080
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#define LINE_CTL_AUI_ONLY 0x0100
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#define LINE_CTL_10BASET 0x0000
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#define LINE_CTL_AUTO_SEL 0x0200
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/* Test Control Register */
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#define TEST_CTL_DIS_LT 0x0080
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#define TEST_CTL_ENDEC_LP 0x0200
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#define TEST_CTL_AUI_LOOP 0x0400
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#define TEST_CTL_DIS_BKOFF 0x0800
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#define TEST_CTL_FDX 0x4000
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/* Receiver Configuration Register */
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#define RX_CFG_SKIP 0x0040
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#define RX_CFG_RX_OK_IE 0x0100
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#define RX_CFG_RX_DMA_ONLY 0x0200
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#define RX_CFG_CRC_ERR_IE 0x1000
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#define RX_CFG_RUNT_IE 0x2000
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#define RX_CFG_X_DATA_IE 0x4000
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#define RX_CFG_ALL_IE 0x7100
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/* Receiver Event Register */
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#define RX_EVENT_DRIBBLE 0x0080
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#define RX_EVENT_RX_OK 0x0100
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#define RX_EVENT_IND_ADDR 0x0400
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#define RX_EVENT_BCAST 0x0800
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#define RX_EVENT_CRC_ERR 0x1000
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#define RX_EVENT_RUNT 0x2000
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#define RX_EVENT_X_DATA 0x4000
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/* Receiver Control Register */
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#define RX_CTL_INDHASH_A 0x0040
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#define RX_CTL_PROMISC_A 0x0080
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#define RX_CTL_RX_OK_A 0x0100
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#define RX_CTL_MCAST_A 0x0200
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#define RX_CTL_IND_A 0x0400
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#define RX_CTL_BCAST_A 0x0800
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#define RX_CTL_CRC_ERR_A 0x1000
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#define RX_CTL_RUNT_A 0x2000
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#define RX_CTL_X_DATA_A 0x4000
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/* Transmit Configuration Register */
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#define TX_CFG_LOSS_CRS_IE 0x0040
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#define TX_CFG_SQE_ERR_IE 0x0080
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#define TX_CFG_TX_OK_IE 0x0100
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#define TX_CFG_OUT_WIN_IE 0x0200
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#define TX_CFG_JABBER_IE 0x0400
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#define TX_CFG_16_COLL_IE 0x8000
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#define TX_CFG_ALL_IE 0x8FC0
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/* Transmit Configuration Register */
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#define TX_EVENT_LOSS_CRS 0x0040
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#define TX_EVENT_SQE_ERR 0x0080
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#define TX_EVENT_TX_OK 0x0100
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#define TX_EVENT_OUT_WIN 0x0200
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#define TX_EVENT_JABBER 0x0400
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#define TX_EVENT_COLL_MASK 0x7800
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#define TX_EVENT_16_COLL 0x8000
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/* Transmit Command Register */
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#define TX_CMD_START_5 0x0000
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#define TX_CMD_START_381 0x0080
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#define TX_CMD_START_1021 0x0040
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#define TX_CMD_START_ALL 0x00C0
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#define TX_CMD_FORCE 0x0100
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#define TX_CMD_ONE_COLL 0x0200
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#define TX_CMD_NO_CRC 0x1000
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#define TX_CMD_NO_PAD 0x2000
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/* Buffer Configuration Register */
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#define BUF_CFG_SW_INT 0x0040
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#define BUF_CFG_RX_DMA_IE 0x0080
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#define BUF_CFG_RDY4TX_IE 0x0100
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#define BUF_CFG_RX_MISS_IE 0x0400
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#define BUF_CFG_TX_UNDR_IE 0x0200
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#define BUF_CFG_RX_128_IE 0x0800
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#define BUF_CFG_TX_COL_OVER_IE 0x1000
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#define BUF_CFG_RX_MISS_OVER_IE 0x2000
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#define BUF_CFG_RX_DEST_IE 0x8000
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/* Buffer Event Register */
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#define BUF_EVENT_SW_INT 0x0040
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#define BUF_EVENT_RX_DMA 0x0080
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#define BUF_EVENT_RDY4TX 0x0100
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#define BUF_EVENT_TX_UNDR 0x0200
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#define BUF_EVENT_RX_MISS 0x0400
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#define BUF_EVENT_RX_128 0x0800
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#define BUF_EVENT_RX_DEST 0x8000
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/* Autonegotiation Control Register */
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#define AUTOCTL_NEG_NOW 0x0040
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#define AUTOCTL_ALLOW_FDX 0x0080
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#define AUTOCTL_NEG_ENABLE 0x0100
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#define AUTOCTL_NLP_ENABLE 0x0200
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#define AUTOCTL_FORCE_FDX 0x8000
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/* Autonegotiation Status Register */
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#define AUTOST_NEG_BUSY 0x0080
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#define AUTOST_FLP_LINK 0x0100
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#define AUTOST_FLP_LINK_GOOD 0x0800
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#define AUTOST_LINK_FAULT 0x1000
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#define AUTOST_HDX_ACTIVE 0x4000
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#define AUTOST_FDX_ACTIVE 0x8000
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/* ISA Configuration from EEPROM */
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#define ISA_CFG_IRQ_MASK 0x000F
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#define ISA_CFG_USE_SA 0x0080
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#define ISA_CFG_IOCHRDY 0x0100
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#define ISA_CFG_MEM_MODE 0x8000
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/* Memory Base from EEPROM */
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#define MEM_BASE_MASK 0xFFF0
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/* Adpater Configuration from EEPROM */
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#define ADPTR_CFG_MEDIA 0x0060
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#define ADPTR_CFG_10BASET 0x0020
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#define ADPTR_CFG_AUI 0x0040
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#define ADPTR_CFG_10BASE2 0x0060
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#define ADPTR_CFG_DCDC_POL 0x0080
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/* Transmission Control from EEPROM */
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#define XMIT_CTL_FDX 0x8000
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/* Miscellaneous definitions */
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#define MAXLOOP 0x8888
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#define RXBUFCOUNT 16
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#define MC_LOANED 5
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#endif /* _DEV_ISA_CS89X0REG_H_ */
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