187 lines
5.6 KiB
C
187 lines
5.6 KiB
C
/* $NetBSD: pccbbvar.h,v 1.26 2006/06/17 17:06:52 jmcneill Exp $ */
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/*
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* Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by HAYAKAWA Koichi.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* require sys/device.h */
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/* require sys/queue.h */
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/* require sys/callout.h */
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/* require dev/ic/i82365reg.h */
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/* require dev/ic/i82365var.h */
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#ifndef _DEV_PCI_PCCBBVAR_H_
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#define _DEV_PCI_PCCBBVAR_H_
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#define PCIC_FLAG_SOCKETP 0x0001
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#define PCIC_FLAG_CARDP 0x0002
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/* Chipset ID */
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#define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */
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#define CB_TI113X 1 /* TI PCI1130/1131 */
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#define CB_TI12XX 2 /* TI PCI12xx/14xx/44xx/15xx/45xx */
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#define CB_RX5C47X 3 /* RICOH RX5C475/476/477 */
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#define CB_RX5C46X 4 /* RICOH RX5C465/466/467 */
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#define CB_TOPIC95 5 /* Toshiba ToPIC95 */
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#define CB_TOPIC95B 6 /* Toshiba ToPIC95B */
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#define CB_TOPIC97 7 /* Toshiba ToPIC97 */
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#define CB_CIRRUS 8 /* Cirrus Logic CL-PD683X */
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#define CB_TI125X 9 /* TI PCI1250/1251(B)/1450 */
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#define CB_CHIPS_LAST 10 /* Sentinel */
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#if 0
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static char *cb_chipset_name[CB_CHIPS_LAST] = {
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"unknown", "TI 113X", "TI 12XX", "RF5C47X", "RF5C46X", "ToPIC95",
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"ToPIC95B", "ToPIC97", "CL-PD 683X", "TI 125X",
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};
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#endif
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struct pccbb_softc;
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struct pccbb_intrhand_list;
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struct cbb_pcic_handle {
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struct device *ph_parent;
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bus_space_tag_t ph_base_t;
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bus_space_handle_t ph_base_h;
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u_int8_t (*ph_read)(struct cbb_pcic_handle *, int);
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void (*ph_write)(struct cbb_pcic_handle *, int, u_int8_t);
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int sock;
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int vendor;
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int flags;
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int memalloc;
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struct {
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bus_addr_t addr;
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bus_size_t size;
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long offset;
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int kind;
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} mem[PCIC_MEM_WINS];
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int ioalloc;
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struct {
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bus_addr_t addr;
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bus_size_t size;
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int width;
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} io[PCIC_IO_WINS];
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int ih_irq;
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struct device *pcmcia;
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int shutdown;
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};
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struct pccbb_win_chain {
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bus_addr_t wc_start; /* Caution: region [start, end], */
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bus_addr_t wc_end; /* instead of [start, end). */
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int wc_flags;
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bus_space_handle_t wc_handle;
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TAILQ_ENTRY(pccbb_win_chain) wc_list;
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};
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#define PCCBB_MEM_CACHABLE 1
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TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain);
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struct pccbb_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_tag_t sc_memt;
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bus_dma_tag_t sc_dmat;
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#if rbus
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rbus_tag_t sc_rbus_iot; /* rbus for i/o donated from parent */
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rbus_tag_t sc_rbus_memt; /* rbus for mem donated from parent */
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#endif
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bus_space_tag_t sc_base_memt;
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bus_space_handle_t sc_base_memh;
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struct callout sc_insert_ch;
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void *sc_ih; /* interrupt handler */
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struct pci_attach_args sc_pa; /* copy of our attach args */
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int sc_function;
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u_int32_t sc_flags;
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#define CBB_CARDEXIST 0x01
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#define CBB_INSERTING 0x01000000
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#define CBB_16BITCARD 0x04
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#define CBB_32BITCARD 0x08
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#define CBB_MEMHMAPPED 0x02000000
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_tag;
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int sc_chipset; /* chipset id */
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bus_addr_t sc_mem_start; /* CardBus/PCMCIA memory start */
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bus_addr_t sc_mem_end; /* CardBus/PCMCIA memory end */
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bus_addr_t sc_io_start; /* CardBus/PCMCIA io start */
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bus_addr_t sc_io_end; /* CardBus/PCMCIA io end */
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pcireg_t sc_sockbase; /* Socket base register */
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pcireg_t sc_busnum; /* bus number */
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/* CardBus stuff */
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struct cardslot_softc *sc_csc;
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struct pccbb_win_chain_head sc_memwindow;
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struct pccbb_win_chain_head sc_iowindow;
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/* pcmcia stuff */
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struct pcic_handle sc_pcmcia_h;
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pcmcia_chipset_tag_t sc_pct;
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int sc_pcmcia_flags;
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#define PCCBB_PCMCIA_IO_RELOC 0x01 /* IO addr relocatable stuff exists */
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#define PCCBB_PCMCIA_MEM_32 0x02 /* 32-bit memory address ready */
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struct proc *sc_event_thread;
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SIMPLEQ_HEAD(, pcic_event) sc_events;
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int sc_pwrcycle;
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/* interrupt handler list on the bridge */
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LIST_HEAD(, pccbb_intrhand_list) sc_pil;
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int sc_pil_intr_enable; /* can i call intr handler for child device? */
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int sc_pwrmgt_offs; /* Offset for power management capability */
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struct pci_conf_state sc_pciconf;
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pcireg_t sc_ricoh_misc_ctrl;
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};
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/*
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* struct pccbb_intrhand_list holds interrupt handler and argument for
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* child devices.
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*/
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struct pccbb_intrhand_list {
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int (*pil_func)(void *);
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void *pil_arg;
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int pil_level;
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LIST_ENTRY(pccbb_intrhand_list) pil_next;
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};
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void pccbb_intr_route(struct pccbb_softc *sc);
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#endif /* _DEV_PCI_PCCBBREG_H_ */
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