564 lines
13 KiB
C
564 lines
13 KiB
C
/* $NetBSD: if_wpireg.h,v 1.1 2006/08/13 02:21:45 simonb Exp $ */
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/*-
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* Copyright (c) 2006
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* Damien Bergamini <damien.bergamini@free.fr>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#define WPI_TX_RING_COUNT 256
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#define WPI_SVC_RING_COUNT 256
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#define WPI_CMD_RING_COUNT 256
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#define WPI_RX_RING_COUNT 64
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/*
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* Rings must be aligned on a four 4K-pages boundary.
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* I had a hard time figuring this out.
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*/
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#define WPI_RING_DMA_ALIGN 0x4000
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/* maximum scatter/gather */
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#define WPI_MAX_SCATTER 4
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/*
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* Control and status registers.
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*/
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#define WPI_HWCONFIG 0x000
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#define WPI_INTR 0x008
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#define WPI_MASK 0x00c
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#define WPI_INTR_STATUS 0x010
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#define WPI_GPIO_STATUS 0x018
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#define WPI_RESET 0x020
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#define WPI_GPIO_CTL 0x024
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#define WPI_EEPROM_CTL 0x02c
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#define WPI_EEPROM_STATUS 0x030
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#define WPI_UCODE_CLR 0x05c
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#define WPI_TEMPERATURE 0x060
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#define WPI_CHICKEN 0x100
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#define WPI_PLL_CTL 0x20c
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#define WPI_FW_TARGET 0x410
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#define WPI_WRITE_MEM_ADDR 0x444
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#define WPI_READ_MEM_ADDR 0x448
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#define WPI_WRITE_MEM_DATA 0x44c
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#define WPI_READ_MEM_DATA 0x450
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#define WPI_TX_WIDX 0x460
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#define WPI_TX_CTL(qid) (0x940 + (qid) * 8)
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#define WPI_TX_BASE(qid) (0x944 + (qid) * 8)
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#define WPI_TX_DESC(qid) (0x980 + (qid) * 80)
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#define WPI_RX_CONFIG 0xc00
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#define WPI_RX_BASE 0xc04
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#define WPI_RX_WIDX 0xc20
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#define WPI_RX_RIDX_PTR 0xc24
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#define WPI_RX_CTL 0xcc0
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#define WPI_RX_STATUS 0xcc4
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#define WPI_TX_CONFIG(qid) (0xd00 + (qid) * 32)
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#define WPI_TX_CREDIT(qid) (0xd04 + (qid) * 32)
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#define WPI_TX_STATE(qid) (0xd08 + (qid) * 32)
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#define WPI_TX_BASE_PTR 0xe80
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#define WPI_MSG_CONFIG 0xe88
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#define WPI_TX_STATUS 0xe90
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/*
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* NIC internal memory offsets.
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*/
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#define WPI_MEM_MODE 0x2e00
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#define WPI_MEM_RA 0x2e04
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#define WPI_MEM_TXCFG 0x2e10
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#define WPI_MEM_MAGIC4 0x2e14
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#define WPI_MEM_MAGIC5 0x2e20
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#define WPI_MEM_BYPASS1 0x2e2c
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#define WPI_MEM_BYPASS2 0x2e30
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#define WPI_MEM_CLOCK1 0x3004
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#define WPI_MEM_CLOCK2 0x3008
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#define WPI_MEM_POWER 0x300c
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#define WPI_MEM_PCIDEV 0x3010
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#define WPI_MEM_UCODE_CTL 0x3400
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#define WPI_MEM_UCODE_SRC 0x3404
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#define WPI_MEM_UCODE_DST 0x3408
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#define WPI_MEM_UCODE_SIZE 0x340c
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#define WPI_MEM_UCODE_BASE 0x3800
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/* possible flags for register WPI_HWCONFIG */
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#define WPI_HW_ALM_MB (1 << 8)
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#define WPI_HW_ALM_MM (1 << 9)
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#define WPI_HW_SKU_MRC (1 << 10)
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#define WPI_HW_REV_D (1 << 11)
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#define WPI_HW_TYPE_B (1 << 12)
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/* possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR */
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#define WPI_MEM_4 ((sizeof (uint32_t) - 1) << 24)
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/* possible values for WPI_FW_TARGET */
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#define WPI_FW_TEXT 0x00000000
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#define WPI_FW_DATA 0x00800000
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/* possible flags for WPI_GPIO_STATUS */
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#define WPI_POWERED (1 << 9)
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/* possible flags for register WPI_RESET */
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#define WPI_NEVO_RESET (1 << 0)
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#define WPI_SW_RESET (1 << 7)
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#define WPI_MASTER_DISABLED (1 << 8)
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#define WPI_STOP_MASTER (1 << 9)
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/* possible flags for register WPI_GPIO_CTL */
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#define WPI_GPIO_CLOCK (1 << 0)
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#define WPI_GPIO_INIT (1 << 2)
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#define WPI_GPIO_MAC (1 << 3)
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#define WPI_GPIO_SLEEP (1 << 4)
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#define WPI_GPIO_PWR_STATUS 0x07000000
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#define WPI_GPIO_PWR_SLEEP (4 << 24)
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/* possible flags for register WPI_CHICKEN */
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#define WPI_CHICKEN_RXNOLOS (1 << 23)
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/* possible flags for register WPI_PLL_CTL */
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#define WPI_PLL_INIT (1 << 24)
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/* possible flags for register WPI_UCODE_CLR */
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#define WPI_RADIO_OFF (1 << 1)
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#define WPI_DISABLE_CMD (1 << 2)
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/* possible flags for WPI_RX_STATUS */
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#define WPI_RX_IDLE (1 << 24)
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/* possible flags for register WPI_UC_CTL */
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#define WPI_UC_RUN (1 << 30)
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/* possible flags for register WPI_INTR_CSR */
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#define WPI_ALIVE_INTR (1 << 0)
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#define WPI_WAKEUP_INTR (1 << 1)
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#define WPI_SW_ERROR (1 << 25)
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#define WPI_TX_INTR (1 << 27)
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#define WPI_HW_ERROR (1 << 29)
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#define WPI_RX_INTR (1 << 31)
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#define WPI_INTR_MASK \
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(WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \
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WPI_ALIVE_INTR | WPI_WAKEUP_INTR)
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/* possible flags for register WPI_TX_STATUS */
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#define WPI_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16))
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/* possible flags for register WPI_EEPROM_CTL */
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#define WPI_EEPROM_READY (1 << 0)
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/* possible flags for register WPI_EEPROM_STATUS */
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#define WPI_EEPROM_VERSION 0x00000007
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#define WPI_EEPROM_LOCKED 0x00000180
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struct wpi_shared {
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uint32_t txbase[8];
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uint32_t next;
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uint32_t reserved[2];
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} __attribute__((__packed__));
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#define WPI_MAX_SEG_LEN 65520
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struct wpi_tx_desc {
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uint32_t flags;
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#define WPI_PAD32(x) ((((x) + 3) & ~3) - (x))
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struct {
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uint32_t addr;
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uint32_t len;
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} __attribute__((__packed__)) segs[WPI_MAX_SCATTER];
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uint8_t reserved[28];
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} __attribute__((__packed__));
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struct wpi_tx_stat {
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uint8_t nrts;
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uint8_t ntries;
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uint8_t nkill;
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uint8_t rate;
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uint32_t duration;
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uint32_t status;
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} __attribute__((__packed__));
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struct wpi_rx_desc {
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uint32_t len;
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uint8_t type;
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#define WPI_UC_READY 1
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#define WPI_RX_DONE 27
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#define WPI_TX_DONE 28
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#define WPI_START_SCAN 130
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#define WPI_STOP_SCAN 132
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#define WPI_STATE_CHANGED 161
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uint8_t flags;
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uint8_t idx;
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uint8_t qid;
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} __attribute__((__packed__));
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struct wpi_rx_stat {
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uint8_t len;
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#define WPI_STAT_MAXLEN 20
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uint8_t id;
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uint8_t rssi; /* received signal strength */
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#define WPI_RSSI_OFFSET 95
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uint8_t agc; /* access gain control */
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uint16_t signal;
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uint16_t noise;
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} __attribute__((__packed__));
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struct wpi_rx_head {
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uint16_t chan;
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uint16_t flags;
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uint8_t reserved;
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uint8_t rate;
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uint16_t len;
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} __attribute__((__packed__));
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struct wpi_rx_tail {
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uint32_t flags;
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#define WPI_RX_NO_CRC_ERR (1 << 0)
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#define WPI_RX_NO_OVFL_ERR (1 << 1)
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/* shortcut for the above */
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#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR)
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uint64_t tstamp;
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uint32_t tbeacon;
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} __attribute__((__packed__));
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struct wpi_tx_cmd {
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uint8_t code;
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#define WPI_CMD_CONFIGURE 16
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#define WPI_CMD_ASSOCIATE 17
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#define WPI_CMD_SET_WME 19
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#define WPI_CMD_TSF 20
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#define WPI_CMD_ADD_NODE 24
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#define WPI_CMD_TX_DATA 28
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#define WPI_CMD_MRR_SETUP 71
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#define WPI_CMD_SET_LED 72
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#define WPI_CMD_SET_POWER_MODE 119
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#define WPI_CMD_SCAN 128
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#define WPI_CMD_SET_BEACON 145
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#define WPI_CMD_BLUETOOTH 155
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#define WPI_CMD_TXPOWER 176
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uint8_t flags;
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uint8_t idx;
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uint8_t qid;
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uint8_t data[124];
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} __attribute__((__packed__));
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/* structure for WPI_CMD_CONFIGURE */
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struct wpi_config {
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uint8_t myaddr[IEEE80211_ADDR_LEN];
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uint16_t reserved1;
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uint8_t bssid[IEEE80211_ADDR_LEN];
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uint16_t reserved2;
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uint32_t reserved3[2];
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uint8_t mode;
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#define WPI_MODE_HOSTAP 1
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#define WPI_MODE_STA 3
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#define WPI_MODE_IBSS 4
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#define WPI_MODE_MONITOR 6
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uint8_t reserved4[3];
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uint8_t ofdm_mask;
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uint8_t cck_mask;
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uint16_t state;
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#define WPI_STATE_ASSOCIATED 4
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uint32_t flags;
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#define WPI_CONFIG_24GHZ (1 << 0)
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#define WPI_CONFIG_CCK (1 << 1)
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#define WPI_CONFIG_AUTO (1 << 2)
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#define WPI_CONFIG_SHSLOT (1 << 4)
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#define WPI_CONFIG_SHPREAMBLE (1 << 5)
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#define WPI_CONFIG_NODIVERSITY (1 << 7)
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#define WPI_CONFIG_ANTENNA_A (1 << 8)
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#define WPI_CONFIG_ANTENNA_B (1 << 9)
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#define WPI_CONFIG_TSF (1 << 15)
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uint32_t filter;
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#define WPI_FILTER_PROMISC (1 << 0)
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#define WPI_FILTER_CTL (1 << 1)
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#define WPI_FILTER_MULTICAST (1 << 2)
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#define WPI_FILTER_NODECRYPT (1 << 3)
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#define WPI_FILTER_BSS (1 << 5)
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#define WPI_FILTER_BEACON (1 << 6)
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uint8_t chan;
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uint8_t reserved6[3];
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} __attribute__((__packed__));
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/* structure for command WPI_CMD_ASSOCIATE */
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struct wpi_assoc {
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uint32_t flags;
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uint32_t filter;
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uint8_t ofdm_mask;
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uint8_t cck_mask;
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uint16_t reserved;
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} __attribute__((__packed__));
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/* structure for command WPI_CMD_SET_WME */
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struct wpi_wme_setup {
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uint32_t flags;
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struct {
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uint16_t cwmin;
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uint16_t cwmax;
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uint8_t aifsn;
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uint8_t reserved;
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uint16_t txop;
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} __packed ac[WME_NUM_AC];
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} __packed;
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/* structure for command WPI_CMD_TSF */
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struct wpi_cmd_tsf {
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uint64_t tstamp;
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uint16_t bintval;
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uint16_t atim;
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uint32_t binitval;
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uint16_t lintval;
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uint16_t reserved;
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} __attribute__((__packed__));
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/* structure for WPI_CMD_ADD_NODE */
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struct wpi_node {
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uint8_t control;
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#define WPI_NODE_UPDATE (1 << 0)
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uint8_t reserved1[3];
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uint8_t bssid[IEEE80211_ADDR_LEN];
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uint16_t reserved2;
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uint8_t id;
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#define WPI_ID_BSS 0
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#define WPI_ID_BROADCAST 24
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uint8_t sta_mask;
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uint16_t reserved3;
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uint16_t key_flags;
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uint8_t tkip;
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uint8_t reserved4;
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uint16_t ttak[5];
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uint16_t reserved5;
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uint8_t key[IEEE80211_KEYBUF_SIZE];
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uint32_t flags;
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uint32_t mask;
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uint16_t tid;
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uint8_t rate;
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uint8_t reserved6;
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uint8_t add_imm;
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uint8_t del_imm;
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uint16_t add_imm_start;
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} __attribute__((__packed__));
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/* structure for command WPI_CMD_TX_DATA */
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struct wpi_cmd_data {
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uint16_t len;
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uint16_t lnext;
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uint32_t flags;
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#define WPI_TX_NEED_RTS (1 << 1)
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#define WPI_TX_NEED_ACK (1 << 3)
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#define WPI_TX_FULL_TXOP (1 << 7)
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#define WPI_TX_AUTO_SEQ (1 << 13)
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#define WPI_TX_INSERT_TSTAMP (1 << 16)
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uint8_t rate;
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uint8_t id;
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uint8_t tid;
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uint8_t security;
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uint8_t key[IEEE80211_KEYBUF_SIZE];
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uint8_t tkip[IEEE80211_WEP_MICLEN];
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uint32_t fnext;
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uint32_t lifetime;
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uint8_t ofdm_mask;
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uint8_t cck_mask;
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uint8_t rts_ntries;
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uint8_t data_ntries;
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uint16_t timeout;
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uint16_t txop;
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struct ieee80211_frame wh;
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} __attribute__((__packed__));
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/* structure for command WPI_CMD_SET_BEACON */
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struct wpi_cmd_beacon {
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uint16_t len;
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uint16_t reserved1;
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uint32_t flags; /* same as wpi_cmd_data */
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uint8_t rate;
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uint8_t id;
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uint8_t reserved2[30];
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uint32_t lifetime;
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uint8_t ofdm_mask;
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uint8_t cck_mask;
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uint16_t reserved3[3];
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uint16_t tim;
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uint8_t timsz;
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uint8_t reserved4;
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struct ieee80211_frame wh;
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} __attribute__((__packed__));
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/* structure for WPI_CMD_MRR_SETUP */
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struct wpi_mrr_setup {
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uint32_t which;
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#define WPI_MRR_CTL 0
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#define WPI_MRR_DATA 1
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struct {
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uint8_t plcp;
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uint8_t flags;
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uint8_t ntries;
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uint8_t next;
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#define WPI_OFDM6 0
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#define WPI_OFDM54 7
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#define WPI_CCK1 8
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#define WPI_CCK2 9
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#define WPI_CCK11 11
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} __attribute__((__packed__)) rates[WPI_CCK11 + 1];
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} __attribute__((__packed__));
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/* structure for WPI_CMD_SET_LED */
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struct wpi_cmd_led {
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uint32_t unit; /* multiplier (in usecs) */
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uint8_t which;
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#define WPI_LED_ACTIVITY 1
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#define WPI_LED_LINK 2
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uint8_t off;
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uint8_t on;
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uint8_t reserved;
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} __attribute__((__packed__));
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/* structure for WPI_CMD_SET_POWER_MODE */
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struct wpi_power {
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uint32_t flags;
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uint32_t rx_timeout;
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uint32_t tx_timeout;
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uint32_t sleep[5];
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} __attribute__((__packed__));
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/* structure for command WPI_CMD_SCAN */
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struct wpi_scan_hdr {
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uint8_t len;
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uint8_t first;
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uint8_t reserved1;
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uint8_t nchan;
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uint16_t quiet;
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uint16_t threshold;
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uint16_t band;
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#define WPI_SCAN_5GHZ 1
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uint16_t reserved2[5];
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uint32_t flags;
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uint32_t filter;
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uint16_t pbrlen;
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uint16_t reserved4;
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uint32_t magic1;
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uint8_t rate;
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uint8_t id;
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uint16_t reserved5;
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uint32_t reserved6[7];
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uint32_t mask;
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uint32_t reserved7[2];
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uint8_t reserved8;
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uint8_t esslen;
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uint8_t essid[134];
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/* followed by probe request body */
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/* followed by nchan x wpi_scan_chan */
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} __attribute__((__packed__));
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struct wpi_scan_chan {
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uint8_t flags;
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uint8_t chan;
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#define WPI_CHAN_ACTIVE 3
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uint16_t magic; /* XXX */
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uint16_t active; /* msecs */
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uint16_t passive; /* msecs */
|
|
} __attribute__((__packed__));
|
|
|
|
/* structure for WPI_CMD_BLUETOOTH */
|
|
struct wpi_bluetooth {
|
|
uint8_t flags;
|
|
uint8_t lead;
|
|
uint8_t kill;
|
|
uint8_t reserved;
|
|
uint32_t ack;
|
|
uint32_t cts;
|
|
} __attribute__((__packed__));
|
|
|
|
/* structure for command WPI_CMD_TXPOWER */
|
|
struct wpi_txpower {
|
|
uint32_t reserved1;
|
|
uint16_t pwr1[14];
|
|
uint32_t reserved2[2];
|
|
uint16_t pwr2[14];
|
|
uint32_t reserved3[2];
|
|
} __attribute__((__packed__));
|
|
|
|
|
|
/* firmware image header */
|
|
struct wpi_firmware_hdr {
|
|
uint32_t version;
|
|
uint32_t textsz;
|
|
uint32_t datasz;
|
|
uint32_t bootsz;
|
|
} __attribute__((__packed__));
|
|
|
|
/* structure for WPI_UC_READY notification */
|
|
struct wpi_ucode_info {
|
|
uint32_t version;
|
|
uint8_t revision[8];
|
|
uint8_t type;
|
|
uint8_t subtype;
|
|
uint16_t reserved;
|
|
uint32_t logptr;
|
|
uint32_t errorptr;
|
|
uint32_t timestamp;
|
|
uint32_t valid;
|
|
} __attribute__((__packed__));
|
|
|
|
/* structure for WPI_START_SCAN notification */
|
|
struct wpi_start_scan {
|
|
uint64_t tstamp;
|
|
uint32_t tbeacon;
|
|
uint8_t chan;
|
|
uint8_t band;
|
|
uint16_t reserved;
|
|
uint32_t status;
|
|
} __attribute__((__packed__));
|
|
|
|
/* structure for WPI_STOP_SCAN notification */
|
|
struct wpi_stop_scan {
|
|
uint8_t nchan;
|
|
uint8_t status;
|
|
uint8_t reserved;
|
|
uint8_t chan;
|
|
uint64_t tsf;
|
|
} __packed;
|
|
|
|
#define WPI_EEPROM_MAC 0x015
|
|
#define WPI_EEPROM_REVISION 0x035
|
|
#define WPI_EEPROM_CAPABILITIES 0x045
|
|
#define WPI_EEPROM_TYPE 0x04a
|
|
#define WPI_EEPROM_PWR1 0x1ae
|
|
#define WPI_EEPROM_PWR2 0x1bc
|
|
|
|
#define WPI_READ(sc, reg) \
|
|
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
|
|
|
|
#define WPI_WRITE(sc, reg, val) \
|
|
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
|
|
|
|
#define WPI_WRITE_REGION_4(sc, offset, datap, count) \
|
|
bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
|
|
(datap), (count))
|