469 lines
14 KiB
C
469 lines
14 KiB
C
/* $NetBSD: rockchip_cpufreq.c,v 1.3 2015/03/29 22:56:23 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "locators.h"
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#include "act8846pm.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rockchip_cpufreq.c,v 1.3 2015/03/29 22:56:23 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/atomic.h>
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#include <sys/kmem.h>
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#include <sys/xcall.h>
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#include <sys/sysctl.h>
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#include <arm/rockchip/rockchip_reg.h>
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#include <arm/rockchip/rockchip_crureg.h>
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#include <arm/rockchip/rockchip_var.h>
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#include <dev/i2c/act8846.h>
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#include <arm/cortex/a9tmr_var.h>
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static bus_space_tag_t bst = &armv7_generic_bs_tag;
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static bus_space_handle_t cru_bsh;
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static bus_space_handle_t grf_bsh;
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static u_int cpufreq_busy;
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static struct sysctllog *cpufreq_log;
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static int cpufreq_node_target, cpufreq_node_current, cpufreq_node_available;
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static u_int (*cpufreq_set_rate)(u_int);
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static u_int (*cpufreq_get_rate)(void);
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static size_t (*cpufreq_get_available)(u_int *, size_t);
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#define ROCKCHIP_CPUFREQ_MAX 8
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static void rockchip_cpufreq_cb(void *, void *);
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static int rockchip_cpufreq_freq_helper(SYSCTLFN_PROTO);
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static char rockchip_cpufreq_available[ROCKCHIP_CPUFREQ_MAX * 5];
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static u_int rk3188_cpu_set_rate(u_int);
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static u_int rk3188_cpu_get_rate(void);
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static size_t rk3188_cpu_get_available(u_int *, size_t);
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void
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rockchip_cpufreq_init(void)
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{
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const struct sysctlnode *node, *cpunode, *freqnode;
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u_int availfreq[ROCKCHIP_CPUFREQ_MAX];
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size_t nfreq;
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int error;
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bus_space_subregion(bst, rockchip_core1_bsh, ROCKCHIP_CRU_OFFSET,
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ROCKCHIP_CRU_SIZE, &cru_bsh);
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bus_space_subregion(bst, rockchip_core1_bsh, ROCKCHIP_GRF_OFFSET,
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ROCKCHIP_GRF_SIZE, &grf_bsh);
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switch (rockchip_chip_id()) {
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case ROCKCHIP_CHIP_ID_RK3066: /* XXX */
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case ROCKCHIP_CHIP_ID_RK3188:
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case ROCKCHIP_CHIP_ID_RK3188PLUS:
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cpufreq_set_rate = &rk3188_cpu_set_rate;
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cpufreq_get_rate = &rk3188_cpu_get_rate;
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cpufreq_get_available = &rk3188_cpu_get_available;
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break;
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default:
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return;
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}
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nfreq = cpufreq_get_available(availfreq, ROCKCHIP_CPUFREQ_MAX);
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if (nfreq == 0)
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return;
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KASSERT(nfreq <= ROCKCHIP_CPUFREQ_MAX);
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for (int i = 0; i < nfreq; i++) {
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char buf[6];
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snprintf(buf, sizeof(buf), i ? " %u" : "%u", availfreq[i]);
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strcat(rockchip_cpufreq_available, buf);
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}
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error = sysctl_createv(&cpufreq_log, 0, NULL, &node,
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CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL,
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NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL);
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if (error)
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goto sysctl_failed;
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error = sysctl_createv(&cpufreq_log, 0, &node, &cpunode,
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0, CTLTYPE_NODE, "cpu", NULL,
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NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
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if (error)
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goto sysctl_failed;
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error = sysctl_createv(&cpufreq_log, 0, &cpunode, &freqnode,
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0, CTLTYPE_NODE, "frequency", NULL,
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NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL);
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if (error)
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goto sysctl_failed;
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error = sysctl_createv(&cpufreq_log, 0, &freqnode, &node,
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CTLFLAG_READWRITE, CTLTYPE_INT, "target", NULL,
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rockchip_cpufreq_freq_helper, 0, NULL, 0,
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CTL_CREATE, CTL_EOL);
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if (error)
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goto sysctl_failed;
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cpufreq_node_target = node->sysctl_num;
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error = sysctl_createv(&cpufreq_log, 0, &freqnode, &node,
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CTLFLAG_READWRITE, CTLTYPE_INT, "current", NULL,
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rockchip_cpufreq_freq_helper, 0, NULL, 0,
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CTL_CREATE, CTL_EOL);
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if (error)
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goto sysctl_failed;
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cpufreq_node_current = node->sysctl_num;
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error = sysctl_createv(&cpufreq_log, 0, &freqnode, &node,
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0, CTLTYPE_STRING, "available", NULL,
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NULL, 0, rockchip_cpufreq_available, 0,
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CTL_CREATE, CTL_EOL);
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if (error)
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goto sysctl_failed;
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cpufreq_node_available = node->sysctl_num;
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return;
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sysctl_failed:
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aprint_error("cpufreq: couldn't create sysctl nodes (%d)\n", error);
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sysctl_teardown(&cpufreq_log);
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}
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static void
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rockchip_cpufreq_cb(void *arg1, void *arg2)
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{
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struct cpu_info *ci = curcpu();
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ci->ci_data.cpu_cc_freq = cpufreq_get_rate() * 1000000;
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}
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static int
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rockchip_cpufreq_freq_helper(SYSCTLFN_ARGS)
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{
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struct sysctlnode node;
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int fq, oldfq = 0, error;
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uint64_t xc;
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node = *rnode;
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node.sysctl_data = &fq;
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fq = cpufreq_get_rate();
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if (rnode->sysctl_num == cpufreq_node_target)
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oldfq = fq;
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error = sysctl_lookup(SYSCTLFN_CALL(&node));
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if (error || newp == NULL)
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return error;
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if (fq == oldfq || rnode->sysctl_num != cpufreq_node_target)
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return 0;
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if (atomic_cas_uint(&cpufreq_busy, 0, 1) != 0)
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return EBUSY;
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error = cpufreq_set_rate(fq);
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if (error == 0) {
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xc = xc_broadcast(0, rockchip_cpufreq_cb, NULL, NULL);
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xc_wait(xc);
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pmf_event_inject(NULL, PMFE_SPEED_CHANGED);
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}
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atomic_dec_uint(&cpufreq_busy);
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return error;
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}
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/*
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* RK3188 / RK3188+
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*/
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struct rk3188_apll_rate {
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u_int rate;
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u_int nr, nf, no;
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u_int core_div, core_periph_div, core_axi_div;
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u_int aclk_div, hclk_div, pclk_div, ahb2apb_div;
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u_int voltage;
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};
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#define RK3188_RATE(_r, _nf, _no, _p, _a, _aclk, _hclk, _pclk, _ahb2apb, _v) \
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{ .rate = (_r) * 1000000, .nr = 1, .nf = (_nf), .no = (_no), \
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.core_div = 1, .core_periph_div = (_p), .core_axi_div = (_a), \
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.aclk_div = (_aclk), .hclk_div = (_hclk), .pclk_div = (_pclk), \
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.ahb2apb_div = (_ahb2apb), .voltage = (_v) }
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static const struct rk3188_apll_rate rk3188_apll_rates[] = {
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RK3188_RATE(1608, 67, 1, 8, 4, 4, 2, 4, 2, 1350),
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RK3188_RATE(1416, 59, 1, 8, 4, 4, 2, 4, 2, 1250),
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RK3188_RATE(1200, 50, 1, 8, 4, 4, 2, 4, 2, 1200),
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RK3188_RATE(1008, 42, 1, 8, 4, 3, 2, 4, 2, 1075),
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RK3188_RATE( 816, 68, 2, 8, 4, 3, 2, 4, 2, 1000),
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RK3188_RATE( 600, 50, 2, 4, 4, 3, 2, 4, 2, 1000),
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};
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#define GRF_STATUS0_REG 0x015c
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#define GRF_STATUS0_APLL_LOCK __BIT(5)
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#define RK3188_GRF_STATUS0_REG 0x00ac
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#define RK3188_GRF_STATUS0_APLL_LOCK __BIT(6)
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static size_t
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rk3188_cpu_get_available(u_int *pavail, size_t maxavail)
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{
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u_int n;
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KASSERT(__arraycount(rk3188_apll_rates) <= maxavail);
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for (n = 0; n < __arraycount(rk3188_apll_rates); n++) {
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pavail[n] = rk3188_apll_rates[n].rate / 1000000;
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}
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return __arraycount(rk3188_apll_rates);
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}
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static u_int
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rk3188_cpu_get_rate(void)
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{
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return rockchip_cpu_get_rate() / 1000000;
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}
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static u_int
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rk3188_cpu_set_rate(u_int rate)
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{
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const struct rk3188_apll_rate *r = NULL;
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uint32_t apll_con0, apll_con1, apll_con2, clksel0_con, clksel1_con;
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uint32_t reset_mask, reset, status0_reg, status0_apll_lock;
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u_int cpu_aclk_div_con;
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u_int old_rate = rk3188_cpu_get_rate();
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u_int new_rate;
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#if NACT8846PM > 0
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device_t pmic;
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struct act8846_ctrl *dcdc3;
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pmic = device_find_by_driver_unit("act8846pm", 0);
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if (pmic == NULL) {
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printf("%s: no PMIC driver found\n", __func__);
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return ENXIO;
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}
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dcdc3 = act8846_lookup(pmic, "DCDC3");
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KASSERT(dcdc3 != NULL);
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#endif
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("%s: rate=%u\n", __func__, rate);
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#endif
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/* Pick the closest rate (nearest 100MHz increment) */
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for (int i = 0; i < __arraycount(rk3188_apll_rates); i++) {
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u_int arate = ((rk3188_apll_rates[i].rate / 1000000) + 50)
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/ 100 * 100;
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if (arate <= rate) {
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r = &rk3188_apll_rates[i];
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break;
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}
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}
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if (r == NULL) {
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("CPU: No matching rate found for %u MHz\n", rate);
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#endif
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return EINVAL;
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}
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switch (rockchip_chip_id()) {
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case ROCKCHIP_CHIP_ID_RK3066:
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case ROCKCHIP_CHIP_ID_RK3188PLUS:
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reset_mask = CRU_PLL_CON3_RESET_MASK;
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reset = CRU_PLL_CON3_RESET;
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apll_con0 = CRU_PLL_CON0_CLKR_MASK | CRU_PLL_CON0_CLKOD_MASK;
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apll_con0 |= __SHIFTIN(r->nr - 1, CRU_PLL_CON0_CLKR);
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apll_con0 |= __SHIFTIN(r->no - 1, CRU_PLL_CON0_CLKOD);
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apll_con1 = CRU_PLL_CON1_CLKF_MASK;
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apll_con1 |= __SHIFTIN(r->nf - 1, CRU_PLL_CON1_CLKF);
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apll_con2 = CRU_PLL_CON2_BWADJ_MASK;
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apll_con2 |= __SHIFTIN(r->nf >> 1, CRU_PLL_CON2_BWADJ);
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break;
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case ROCKCHIP_CHIP_ID_RK3188:
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reset_mask = CRU_PLL_CON3_POWER_DOWN_MASK;
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reset = CRU_PLL_CON3_POWER_DOWN;
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apll_con0 =
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CRU_PLL_CON0_CLKR_MASK | RK3188_CRU_PLL_CON0_CLKOD_MASK;
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apll_con0 |= __SHIFTIN(r->nr - 1, CRU_PLL_CON0_CLKR);
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apll_con0 |= __SHIFTIN(r->no - 1, RK3188_CRU_PLL_CON0_CLKOD);
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apll_con1 = RK3188_CRU_PLL_CON1_CLKF_MASK;
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apll_con1 |= __SHIFTIN(r->nf - 1, RK3188_CRU_PLL_CON1_CLKF);
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apll_con2 = 0;
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break;
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default:
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return EINVAL;
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}
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switch (r->core_axi_div) {
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case 1: cpu_aclk_div_con = 0; break;
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case 2: cpu_aclk_div_con = 1; break;
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case 3: cpu_aclk_div_con = 2; break;
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case 4: cpu_aclk_div_con = 3; break;
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case 8: cpu_aclk_div_con = 4; break;
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default: panic("bad core_axi_div");
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}
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switch (rockchip_chip_id()) {
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case ROCKCHIP_CHIP_ID_RK3066:
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clksel0_con = CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
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CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK;
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clksel0_con |= __SHIFTIN(r->core_div - 1,
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CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
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clksel0_con |= __SHIFTIN(ffs(r->core_periph_div) - 2,
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CRU_CLKSEL_CON0_CORE_PERI_DIV_CON);
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clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
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CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
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CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK |
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CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK;
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clksel1_con |= __SHIFTIN(ffs(r->ahb2apb_div) - 1,
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CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
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clksel1_con |= __SHIFTIN(ffs(r->hclk_div) - 1,
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CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON);
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clksel1_con |= __SHIFTIN(ffs(r->pclk_div) - 1,
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CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON);
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clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
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CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
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status0_reg = GRF_STATUS0_REG;
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status0_apll_lock = GRF_STATUS0_APLL_LOCK;
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break;
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case ROCKCHIP_CHIP_ID_RK3188:
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case ROCKCHIP_CHIP_ID_RK3188PLUS:
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clksel0_con = RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
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CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK;
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clksel0_con |= __SHIFTIN(r->core_div - 1,
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RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
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clksel0_con |= __SHIFTIN(ffs(r->core_periph_div) - 2,
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CRU_CLKSEL_CON0_CORE_PERI_DIV_CON);
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clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
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CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
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CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK |
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RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK;
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clksel1_con |= __SHIFTIN(ffs(r->ahb2apb_div) - 1,
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CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
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clksel1_con |= __SHIFTIN(ffs(r->hclk_div) - 1,
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CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON);
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clksel1_con |= __SHIFTIN(ffs(r->pclk_div) - 1,
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CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON);
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clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
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RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
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status0_reg = RK3188_GRF_STATUS0_REG;
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status0_apll_lock = RK3188_GRF_STATUS0_APLL_LOCK;
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break;
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default:
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return EINVAL;
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}
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#ifdef ROCKCHIP_CLOCK_DEBUG
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printf("%s: Set frequency to %u MHz...\n", __func__, r->rate);
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printf("before: APLL_CON0: %#x\n",
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bus_space_read_4(bst, cru_bsh, CRU_APLL_CON0_REG));
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printf("before: APLL_CON1: %#x\n",
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bus_space_read_4(bst, cru_bsh, CRU_APLL_CON1_REG));
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printf("before: CLKSEL0_CON: %#x\n",
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bus_space_read_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(0)));
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printf("before: CLKSEL1_CON: %#x\n",
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bus_space_read_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(1)));
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#endif
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new_rate = r->rate / 1000000;
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if (new_rate > old_rate) {
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#if NACT8846PM > 0
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act8846_set_voltage(dcdc3, r->voltage, r->voltage);
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#endif
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}
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bus_space_write_4(bst, cru_bsh, CRU_MODE_CON_REG,
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CRU_MODE_CON_APLL_WORK_MODE_MASK |
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__SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_SLOW,
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CRU_MODE_CON_APLL_WORK_MODE));
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/* Power down */
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bus_space_write_4(bst, cru_bsh, CRU_APLL_CON3_REG, reset_mask | reset);
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/* Update APLL regs */
|
|
bus_space_write_4(bst, cru_bsh, CRU_APLL_CON0_REG, apll_con0);
|
|
bus_space_write_4(bst, cru_bsh, CRU_APLL_CON1_REG, apll_con1);
|
|
if (apll_con2)
|
|
bus_space_write_4(bst, cru_bsh, CRU_APLL_CON2_REG, apll_con2);
|
|
|
|
for (volatile int i = 5000; i >= 0; i--)
|
|
;
|
|
|
|
/* Power up */
|
|
bus_space_write_4(bst, cru_bsh, CRU_APLL_CON3_REG, reset_mask);
|
|
|
|
/* Wait for PLL lock */
|
|
#ifdef ROCKCHIP_CLOCK_DEBUG
|
|
printf("%s: Waiting for PLL lock...\n", __func__);
|
|
#endif
|
|
for (volatile int i = 50000; i >= 0; i--)
|
|
;
|
|
int retry = ROCKCHIP_REF_FREQ;
|
|
while (--retry > 0) {
|
|
uint32_t status = bus_space_read_4(bst, grf_bsh, status0_reg);
|
|
if (status & status0_apll_lock)
|
|
break;
|
|
}
|
|
if (retry == 0)
|
|
printf("%s: PLL lock timeout\n", __func__);
|
|
|
|
/* Update CLKSEL regs */
|
|
bus_space_write_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(0), clksel0_con);
|
|
bus_space_write_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(1), clksel1_con);
|
|
|
|
/* Slow -> Normal mode */
|
|
bus_space_write_4(bst, cru_bsh, CRU_MODE_CON_REG,
|
|
CRU_MODE_CON_APLL_WORK_MODE_MASK |
|
|
__SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_NORMAL,
|
|
CRU_MODE_CON_APLL_WORK_MODE));
|
|
|
|
#ifdef ROCKCHIP_CLOCK_DEBUG
|
|
printf("after: APLL_CON0: %#x\n",
|
|
bus_space_read_4(bst, cru_bsh, CRU_APLL_CON0_REG));
|
|
printf("after: APLL_CON1: %#x\n",
|
|
bus_space_read_4(bst, cru_bsh, CRU_APLL_CON1_REG));
|
|
printf("after: CLKSEL0_CON: %#x\n",
|
|
bus_space_read_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(0)));
|
|
printf("after: CLKSEL1_CON: %#x\n",
|
|
bus_space_read_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(1)));
|
|
#endif
|
|
|
|
a9tmr_update_freq(rockchip_a9periph_get_rate());
|
|
|
|
#if NACT8846PM > 0
|
|
if (new_rate < old_rate) {
|
|
act8846_set_voltage(dcdc3, r->voltage, r->voltage);
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|