211 lines
6.8 KiB
C
211 lines
6.8 KiB
C
/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "locators.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: awin_twi.c,v 1.6 2014/12/05 15:25:27 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/gttwsivar.h>
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#include <arm/allwinner/awin_reg.h>
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#include <arm/allwinner/awin_var.h>
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#define TWI_CCR_REG 0x14
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#define TWI_CCR_CLK_M __BITS(6,3)
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#define TWI_CCR_CLK_N __BITS(2,0)
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static int awin_twi_match(device_t, cfdata_t, void *);
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static void awin_twi_attach(device_t, device_t, void *);
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struct awin_twi_softc {
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struct gttwsi_softc asc_sc;
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void *asc_ih;
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};
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static int awin_twi_ports;
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static const struct awin_gpio_pinset awin_twi_pinsets[] = {
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[0] = { 'B', AWIN_PIO_PB_TWI0_FUNC, AWIN_PIO_PB_TWI0_PINS },
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[1] = { 'B', AWIN_PIO_PB_TWI1_FUNC, AWIN_PIO_PB_TWI1_PINS },
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[2] = { 'B', AWIN_PIO_PB_TWI2_FUNC, AWIN_PIO_PB_TWI2_PINS },
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[3] = { 'I', AWIN_PIO_PI_TWI3_FUNC, AWIN_PIO_PI_TWI3_PINS },
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[4] = { 'I', AWIN_PIO_PI_TWI4_FUNC, AWIN_PIO_PI_TWI4_PINS },
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};
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static const struct awin_gpio_pinset awin_twi_pinsets_a31[] = {
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[0] = { 'H', AWIN_A31_PIO_PH_TWI0_FUNC, AWIN_A31_PIO_PH_TWI0_PINS },
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[1] = { 'H', AWIN_A31_PIO_PH_TWI1_FUNC, AWIN_A31_PIO_PH_TWI1_PINS },
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[2] = { 'H', AWIN_A31_PIO_PH_TWI2_FUNC, AWIN_A31_PIO_PH_TWI2_PINS },
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[3] = { 'B', AWIN_A31_PIO_PB_TWI3_FUNC, AWIN_A31_PIO_PB_TWI3_PINS },
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};
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static const struct awin_gpio_pinset awin_twi_pinsets_a80[] = {
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[0] = { 'H', AWIN_A80_PIO_PH_TWI0_FUNC, AWIN_A80_PIO_PH_TWI0_PINS },
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[1] = { 'H', AWIN_A80_PIO_PH_TWI1_FUNC, AWIN_A80_PIO_PH_TWI1_PINS },
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[2] = { 'H', AWIN_A80_PIO_PH_TWI2_FUNC, AWIN_A80_PIO_PH_TWI2_PINS },
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[3] = { 'G', AWIN_A80_PIO_PG_TWI3_FUNC, AWIN_A80_PIO_PG_TWI3_PINS },
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[4] = { 'B', AWIN_A80_PIO_PB_TWI4_FUNC, AWIN_A80_PIO_PB_TWI4_PINS },
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};
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CFATTACH_DECL_NEW(awin_twi, sizeof(struct awin_twi_softc),
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awin_twi_match, awin_twi_attach, NULL, NULL);
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static int
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awin_twi_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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unsigned int port = loc->loc_port;
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KASSERT(!strcmp(cf->cf_name, loc->loc_name));
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KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT
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|| cf->cf_loc[AWINIOCF_PORT] == loc->loc_port);
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KASSERT((awin_twi_ports & __BIT(loc->loc_port)) == 0);
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/*
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* We don't have alternative mappings so if one is requested
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* fail the match.
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*/
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if (cf->cf_flags & 1)
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return 0;
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if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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if (!awin_gpio_pinset_available(&awin_twi_pinsets_a31[port]))
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return 0;
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} else if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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if (!awin_gpio_pinset_available(&awin_twi_pinsets_a80[port]))
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return 0;
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} else {
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if (!awin_gpio_pinset_available(&awin_twi_pinsets[port]))
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return 0;
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}
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return 1;
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}
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static void
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awin_twi_attach(device_t parent, device_t self, void *aux)
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{
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struct awin_twi_softc * const asc = device_private(self);
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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prop_dictionary_t cfg = device_properties(self);
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bus_space_handle_t bsh;
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uint32_t ccr;
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awin_twi_ports |= __BIT(loc->loc_port);
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/*
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* Acquire the PIO pins needed for the TWI port.
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*/
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if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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awin_gpio_pinset_acquire(&awin_twi_pinsets_a31[loc->loc_port]);
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} else if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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awin_gpio_pinset_acquire(&awin_twi_pinsets_a80[loc->loc_port]);
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} else {
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awin_gpio_pinset_acquire(&awin_twi_pinsets[loc->loc_port]);
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}
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/*
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* Clock gating, soft reset
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*/
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if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_REG,
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AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI0 << loc->loc_port, 0);
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_REG,
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AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI0 << loc->loc_port, 0);
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} else {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_APB1_GATING_REG,
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AWIN_APB_GATING1_TWI0 << loc->loc_port, 0);
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if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A31_APB2_RESET_REG,
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AWIN_A31_APB2_RESET_TWI0_RST << loc->loc_port, 0);
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}
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}
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/*
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* Get a bus space handle for this TWI port.
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*/
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bus_space_subregion(aio->aio_core_bst, aio->aio_core_bsh,
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loc->loc_offset, loc->loc_size, &bsh);
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/*
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* A31/A80 quirk
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*/
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switch (awin_chip_id()) {
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case AWIN_CHIP_ID_A31:
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case AWIN_CHIP_ID_A80:
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prop_dictionary_set_bool(cfg, "iflg-rwc", true);
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break;
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}
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/*
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* Set clock rate to 100kHz. From the datasheet:
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* For 100Khz standard speed 2Wire, CLK_N=2, CLK_M=11
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* F0=48M/2^2=12Mhz, F1=F0/(10*(11+1)) = 0.1Mhz
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*/
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ccr = __SHIFTIN(11, TWI_CCR_CLK_M) | __SHIFTIN(2, TWI_CCR_CLK_N);
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bus_space_write_4(aio->aio_core_bst, bsh, TWI_CCR_REG, ccr);
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/*
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* Do the MI attach
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*/
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gttwsi_attach_subr(self, aio->aio_core_bst, bsh);
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/*
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* Establish interrupt for it
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*/
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asc->asc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_LEVEL,
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gttwsi_intr, &asc->asc_sc);
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if (asc->asc_ih == NULL) {
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aprint_error_dev(self, "failed to establish interrupt %d\n",
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loc->loc_intr);
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return;
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}
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aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
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/*
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* Configure its children
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*/
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gttwsi_config_children(self);
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}
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