530 lines
16 KiB
C
530 lines
16 KiB
C
/* $NetBSD: if_ie_mbmem.c,v 1.3 2001/06/27 17:32:44 fredette Exp $ */
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/*-
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* Copyright (c) 1995 Charles D. Cranor
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles D. Cranor.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Converted to SUN ie driver by Charles D. Cranor,
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* October 1994, January 1995.
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*/
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/*
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* The i82586 is a very painful chip, found in sun2's, sun3's, sun-4/100's
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* sun-4/200's, and VME based suns. The byte order is all wrong for a
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* SUN, making life difficult. Programming this chip is mostly the same,
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* but certain details differ from system to system. This driver is
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* written so that different "ie" interfaces can be controled by the same
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* driver.
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*/
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/*
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* programming notes:
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*
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* the ie chip operates in a 24 bit address space.
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*
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* most ie interfaces appear to be divided into two parts:
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* - generic 586 stuff
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* - board specific
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*
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* generic:
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* the generic stuff of the ie chip is all done with data structures
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* that live in the chip's memory address space. the chip expects
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* its main data structure (the sys conf ptr -- SCP) to be at a fixed
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* address in its 24 bit space: 0xfffff4
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*
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* the SCP points to another structure called the ISCP.
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* the ISCP points to another structure called the SCB.
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* the SCB has a status field, a linked list of "commands", and
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* a linked list of "receive buffers". these are data structures that
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* live in memory, not registers.
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*
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* board:
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* to get the chip to do anything, you first put a command in the
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* command data structure list. then you have to signal "attention"
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* to the chip to get it to look at the command. how you
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* signal attention depends on what board you have... on PC's
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* there is an i/o port number to do this, on sun's there is a
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* register bit you toggle.
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*
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* to get data from the chip you program it to interrupt...
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*
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*
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* sun issues:
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*
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* there are 3 kinds of sun "ie" interfaces:
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* 1 - a VME/multibus card
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* 2 - an on-board interface (sun3's, sun-4/100's, and sun-4/200's)
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* 3 - another VME board called the 3E
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*
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* the VME boards lives in vme16 space. only 16 and 8 bit accesses
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* are allowed, so functions that copy data must be aware of this.
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*
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* the chip is an intel chip. this means that the byte order
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* on all the "short"s in the chip's data structures is wrong.
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* so, constants described in the intel docs are swapped for the sun.
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* that means that any buffer pointers you give the chip must be
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* swapped to intel format. yuck.
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*
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* VME/multibus interface:
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* for the multibus interface the board ignores the top 4 bits
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* of the chip address. the multibus interface has its own
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* MMU like page map (without protections or valid bits, etc).
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* there are 256 pages of physical memory on the board (each page
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* is 1024 bytes). There are 1024 slots in the page map. so,
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* a 1024 byte page takes up 10 bits of address for the offset,
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* and if there are 1024 slots in the page that is another 10 bits
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* of the address. That makes a 20 bit address, and as stated
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* earlier the board ignores the top 4 bits, so that accounts
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* for all 24 bits of address.
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*
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* Note that the last entry of the page map maps the top of the
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* 24 bit address space and that the SCP is supposed to be at
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* 0xfffff4 (taking into account allignment). so,
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* for multibus, that entry in the page map has to be used for the SCP.
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*
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* The page map effects BOTH how the ie chip sees the
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* memory, and how the host sees it.
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*
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* The page map is part of the "register" area of the board
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*
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* The page map to control where ram appears in the address space.
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* We choose to have RAM start at 0 in the 24 bit address space.
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*
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* to get the phyiscal address of the board's RAM you must take the
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* top 12 bits of the physical address of the register address and
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* or in the 4 bits from the status word as bits 17-20 (remember that
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* the board ignores the chip's top 4 address lines). For example:
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* if the register is @ 0xffe88000, then the top 12 bits are 0xffe00000.
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* to get the 4 bits from the status word just do status & IEMBMEM_HADDR.
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* suppose the value is "4". Then just shift it left 16 bits to get
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* it into bits 17-20 (e.g. 0x40000). Then or it to get the
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* address of RAM (in our example: 0xffe40000). see the attach routine!
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*
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*
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* on-board interface:
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*
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* on the onboard ie interface the 24 bit address space is hardwired
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* to be 0xff000000 -> 0xffffffff of KVA. this means that sc_iobase
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* will be 0xff000000. sc_maddr will be where ever we allocate RAM
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* in KVA. note that since the SCP is at a fixed address it means
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* that we have to allocate a fixed KVA for the SCP.
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* <fill in useful info later>
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*
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*
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* VME3E interface:
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*
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* <fill in useful info later>
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/protosw.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_types.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#include <machine/autoconf.h>
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#include <machine/idprom.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/cpu.h>
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#include <dev/ic/i82586reg.h>
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#include <dev/ic/i82586var.h>
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#include "locators.h"
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/*
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* VME/multibus definitions
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*/
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#define IEMBMEM_PAGESIZE 1024 /* bytes */
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#define IEMBMEM_PAGSHIFT 10 /* bits */
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#define IEMBMEM_NPAGES 256 /* number of pages on chip */
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#define IEMBMEM_MAPSZ 1024 /* number of entries in the map */
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/*
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* PTE for the page map
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*/
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#define IEMBMEM_SBORDR 0x8000 /* sun byte order */
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#define IEMBMEM_IBORDR 0x0000 /* intel byte ordr */
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#define IEMBMEM_P2MEM 0x2000 /* memory is on P2 */
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#define IEMBMEM_OBMEM 0x0000 /* memory is on board */
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#define IEMBMEM_PGMASK 0x0fff /* gives the physical page frame number */
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struct iembmem {
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u_int16_t pgmap[IEMBMEM_MAPSZ];
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u_int16_t xxx[32]; /* prom */
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u_int16_t status; /* see below for bits */
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u_int16_t xxx2; /* filler */
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u_int16_t pectrl; /* parity control (see below) */
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u_int16_t peaddr; /* low 16 bits of address */
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};
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/*
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* status bits
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*/
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#define IEMBMEM_RESET 0x8000 /* reset board */
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#define IEMBMEM_ONAIR 0x4000 /* go out of loopback 'on-air' */
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#define IEMBMEM_ATTEN 0x2000 /* attention */
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#define IEMBMEM_IENAB 0x1000 /* interrupt enable */
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#define IEMBMEM_PEINT 0x0800 /* parity error interrupt enable */
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#define IEMBMEM_PERR 0x0200 /* parity error flag */
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#define IEMBMEM_INT 0x0100 /* interrupt flag */
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#define IEMBMEM_P2EN 0x0020 /* enable p2 bus */
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#define IEMBMEM_256K 0x0010 /* 256kb rams */
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#define IEMBMEM_HADDR 0x000f /* mask for bits 17-20 of address */
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/*
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* parity control
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*/
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#define IEMBMEM_PARACK 0x0100 /* parity error ack */
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#define IEMBMEM_PARSRC 0x0080 /* parity error source */
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#define IEMBMEM_PAREND 0x0040 /* which end of the data got the error */
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#define IEMBMEM_PARADR 0x000f /* mask to get bits 17-20 of parity address */
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/* Supported media */
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static int media[] = {
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IFM_ETHER | IFM_10_2,
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};
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#define NMEDIA (sizeof(media) / sizeof(media[0]))
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/*
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* the 3E board not supported (yet?)
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*/
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static void ie_mbmemreset __P((struct ie_softc *, int));
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static void ie_mbmemattend __P((struct ie_softc *, int));
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static void ie_mbmemrun __P((struct ie_softc *));
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static int ie_mbmemintr __P((struct ie_softc *, int));
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int ie_mbmem_match __P((struct device *, struct cfdata *, void *));
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void ie_mbmem_attach __P((struct device *, struct device *, void *));
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struct ie_mbmem_softc {
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struct ie_softc ie;
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bus_space_tag_t ievt;
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bus_space_handle_t ievh;
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};
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struct cfattach ie_mbmem_ca = {
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sizeof(struct ie_mbmem_softc), ie_mbmem_match, ie_mbmem_attach
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};
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#define read_iev(sc, reg) \
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bus_space_read_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg))
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#define write_iev(sc, reg, val) \
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bus_space_write_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg), val)
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/*
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* MULTIBUS support routines
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*/
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void
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ie_mbmemreset(sc, what)
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struct ie_softc *sc;
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int what;
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{
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struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc;
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write_iev(vsc, status, IEMBMEM_RESET);
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delay(100); /* XXX could be shorter? */
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write_iev(vsc, status, 0);
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}
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void
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ie_mbmemattend(sc, why)
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struct ie_softc *sc;
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int why;
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{
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struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc;
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/* flag! */
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write_iev(vsc, status, read_iev(vsc, status) | IEMBMEM_ATTEN);
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/* down. */
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write_iev(vsc, status, read_iev(vsc, status) & ~IEMBMEM_ATTEN);
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}
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void
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ie_mbmemrun(sc)
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struct ie_softc *sc;
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{
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struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc;
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write_iev(vsc, status, read_iev(vsc, status)
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| IEMBMEM_ONAIR | IEMBMEM_IENAB | IEMBMEM_PEINT);
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}
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int
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ie_mbmemintr(sc, where)
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struct ie_softc *sc;
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int where;
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{
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struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc;
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if (where != INTR_ENTER)
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return (0);
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/*
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* check for parity error
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*/
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if (read_iev(vsc, status) & IEMBMEM_PERR) {
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printf("%s: parity error (ctrl 0x%x @ 0x%02x%04x)\n",
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sc->sc_dev.dv_xname, read_iev(vsc, pectrl),
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read_iev(vsc, pectrl) & IEMBMEM_HADDR,
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read_iev(vsc, peaddr));
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write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEMBMEM_PARACK);
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}
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return (0);
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}
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void ie_mbmemcopyin __P((struct ie_softc *, void *, int, size_t));
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void ie_mbmemcopyout __P((struct ie_softc *, const void *, int, size_t));
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/*
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* Copy board memory to kernel.
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*/
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void
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ie_mbmemcopyin(sc, p, offset, size)
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struct ie_softc *sc;
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void *p;
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int offset;
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size_t size;
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{
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bus_space_copyin(sc->bt, sc->bh, offset, p, size);
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}
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/*
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* Copy from kernel space to board memory.
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*/
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void
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ie_mbmemcopyout(sc, p, offset, size)
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struct ie_softc *sc;
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const void *p;
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int offset;
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size_t size;
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{
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bus_space_copyout(sc->bt, sc->bh, offset, p, size);
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}
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/* read a 16-bit value at BH offset */
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u_int16_t ie_mbmem_read16 __P((struct ie_softc *, int offset));
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/* write a 16-bit value at BH offset */
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void ie_mbmem_write16 __P((struct ie_softc *, int offset, u_int16_t value));
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void ie_mbmem_write24 __P((struct ie_softc *, int offset, int addr));
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u_int16_t
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ie_mbmem_read16(sc, offset)
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struct ie_softc *sc;
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int offset;
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{
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u_int16_t v;
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bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_READ);
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v = bus_space_read_2(sc->bt, sc->bh, offset);
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return (((v&0xff)<<8) | ((v>>8)&0xff));
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}
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void
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ie_mbmem_write16(sc, offset, v)
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struct ie_softc *sc;
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int offset;
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u_int16_t v;
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{
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int v0 = ((((v)&0xff)<<8) | (((v)>>8)&0xff));
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bus_space_write_2(sc->bt, sc->bh, offset, v0);
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bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_WRITE);
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}
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void
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ie_mbmem_write24(sc, offset, addr)
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struct ie_softc *sc;
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int offset;
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int addr;
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{
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u_char *f = (u_char *)&addr;
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u_int16_t v0, v1;
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u_char *t;
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t = (u_char *)&v0;
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t[0] = f[3]; t[1] = f[2];
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bus_space_write_2(sc->bt, sc->bh, offset, v0);
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t = (u_char *)&v1;
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t[0] = f[1]; t[1] = 0;
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bus_space_write_2(sc->bt, sc->bh, offset+2, v1);
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bus_space_barrier(sc->bt, sc->bh, offset, 4, BUS_SPACE_BARRIER_WRITE);
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}
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int
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ie_mbmem_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct mbmem_attach_args *mbma = aux;
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bus_space_handle_t bh;
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int matched;
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/* No default Multibus address. */
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if (mbma->mbma_paddr == -1)
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return(0);
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/* Make sure there is something there... */
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if (bus_space_map(mbma->mbma_bustag, mbma->mbma_paddr, sizeof(struct iembmem),
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0, &bh))
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return (0);
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matched = (bus_space_peek_2(mbma->mbma_bustag, bh, 0, NULL) == 0);
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bus_space_unmap(mbma->mbma_bustag, bh, sizeof(struct iembmem));
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if (!matched)
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return (0);
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/* Default interrupt priority. */
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if (mbma->mbma_pri == -1)
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mbma->mbma_pri = 3;
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return (1);
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}
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void
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ie_mbmem_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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u_int8_t myaddr[ETHER_ADDR_LEN];
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struct ie_mbmem_softc *vsc = (void *) self;
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struct mbmem_attach_args *mbma = aux;
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struct ie_softc *sc;
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bus_size_t memsize;
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bus_addr_t rampaddr;
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int lcv;
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sc = &vsc->ie;
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sc->hwreset = ie_mbmemreset;
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sc->hwinit = ie_mbmemrun;
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sc->chan_attn = ie_mbmemattend;
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sc->intrhook = ie_mbmemintr;
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sc->memcopyout = ie_mbmemcopyout;
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sc->memcopyin = ie_mbmemcopyin;
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sc->ie_bus_barrier = NULL;
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sc->ie_bus_read16 = ie_mbmem_read16;
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sc->ie_bus_write16 = ie_mbmem_write16;
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sc->ie_bus_write24 = ie_mbmem_write24;
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/*
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* There is 64K of memory on the Multibus board.
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* (determined by hardware - NOT configurable!)
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*/
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memsize = 0x10000; /* MEMSIZE 64K */
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/* Map in the board control regs. */
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vsc->ievt = mbma->mbma_bustag;
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if (bus_space_map(mbma->mbma_bustag, mbma->mbma_paddr, sizeof(struct iembmem),
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0, &vsc->ievh))
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panic("ie_mbmem_attach: can't map regs");
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/*
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* Find and map in the board memory.
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*/
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/* top 12 bits */
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rampaddr = mbma->mbma_paddr & 0xfff00000;
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/* 4 more */
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rampaddr = rampaddr | ((read_iev(vsc, status) & IEMBMEM_HADDR) << 16);
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sc->bt = mbma->mbma_bustag;
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if (bus_space_map(mbma->mbma_bustag, rampaddr, memsize, 0, &sc->bh))
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panic("ie_mbmem_attach: can't map mem");
|
|
|
|
write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEMBMEM_PARACK);
|
|
|
|
/*
|
|
* Set up mappings, direct map except for last page
|
|
* which is mapped at zero and at high address (for scp)
|
|
*/
|
|
for (lcv = 0; lcv < IEMBMEM_MAPSZ - 1; lcv++)
|
|
write_iev(vsc, pgmap[lcv], IEMBMEM_SBORDR | IEMBMEM_OBMEM | lcv);
|
|
write_iev(vsc, pgmap[IEMBMEM_MAPSZ - 1], IEMBMEM_SBORDR | IEMBMEM_OBMEM | 0);
|
|
|
|
/* Clear all ram */
|
|
bus_space_set_region_2(sc->bt, sc->bh, 0, 0, memsize/2);
|
|
|
|
/*
|
|
* We use the first page to set up SCP, ICSP and SCB data
|
|
* structures. The remaining pages become the buffer area
|
|
* (managed in i82586.c).
|
|
* SCP is in double-mapped page, so the 586 can see it at
|
|
* the mandatory magic address (IE_SCP_ADDR).
|
|
*/
|
|
sc->scp = (IE_SCP_ADDR & (IEMBMEM_PAGESIZE - 1));
|
|
|
|
/* iscp at location zero */
|
|
sc->iscp = 0;
|
|
|
|
/* scb follows iscp */
|
|
sc->scb = IE_ISCP_SZ;
|
|
|
|
ie_mbmem_write16(sc, IE_ISCP_SCB((long)sc->iscp), sc->scb);
|
|
ie_mbmem_write16(sc, IE_ISCP_BASE((u_long)sc->iscp), 0);
|
|
ie_mbmem_write24(sc, IE_SCP_ISCP((u_long)sc->scp), 0);
|
|
|
|
if (i82586_proberam(sc) == 0) {
|
|
printf(": memory probe failed\n");
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Rest of first page is unused; rest of ram for buffers.
|
|
*/
|
|
sc->buf_area = IEMBMEM_PAGESIZE;
|
|
sc->buf_area_sz = memsize - IEMBMEM_PAGESIZE;
|
|
|
|
sc->do_xmitnopchain = 0;
|
|
|
|
printf("\n%s:", self->dv_xname);
|
|
|
|
/* Set the ethernet address. */
|
|
idprom_etheraddr(myaddr);
|
|
|
|
i82586_attach(sc, "multibus", myaddr, media, NMEDIA, media[0]);
|
|
|
|
bus_intr_establish(mbma->mbma_bustag, mbma->mbma_pri, IPL_NET, 0,
|
|
i82586_intr, sc);
|
|
}
|