118 lines
4.8 KiB
C
118 lines
4.8 KiB
C
/* $NetBSD: vmereg.h,v 1.5 1998/09/19 16:44:59 pk Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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struct vmebusreg {
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volatile u_int32_t vmebus_cr; /* VMEbus control register */
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volatile u_int32_t vmebus_afar; /* VMEbus async fault address */
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volatile u_int32_t vmebus_afsr; /* VMEbus async fault status */
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};
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/* VME bus Register offsets */
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#define VMEBUS_CR_REG 0
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#define VMEBUS_AFAR_REG 4
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#define VMEBUS_AFSR_REG 8
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/* VME Control Register bits */
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#define VMEBUS_CR_C 0x80000000 /* I/O cache enable */
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#define VMEBUS_CR_S 0x40000000 /* VME slave enable */
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#define VMEBUS_CR_L 0x20000000 /* Loopback enable (diagnostic) */
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#define VMEBUS_CR_R 0x10000000 /* VMEbus reset */
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#define VMEBUS_CR_RSVD 0x0ffffff0 /* reserved */
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#define VMEBUS_CR_IMPL 0x0000000f /* VMEbus interface implementation */
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#define VMEBUS_CR_BITS "\177\020" \
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"f\0\4IMPL\0b\34R\0b\35L\0b\36S\0b\37C\0"
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/* VME Asynchronous Fault Status bits */
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#define VMEBUS_AFSR_SZ 0xe0000000 /* Error transaction size */
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#define VMEBUS_AFSR_SZ4 0 /* 4 byte */
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#define VMEBUS_AFSR_SZ1 1 /* 1 byte */
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#define VMEBUS_AFSR_SZ2 2 /* 2 byte */
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#define VMEBUS_AFSR_SZ32 5 /* 32 byte */
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#define VMEBUS_AFSR_TO 0x10000000 /* VME master access time-out */
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#define VMEBUS_AFSR_BERR 0x08000000 /* VME master got BERR */
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#define VMEBUS_AFSR_WB 0x04000000 /* IOC write-back error (if SZ == 32) */
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/* Non-IOC write error (id SZ != 32) */
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#define VMEBUS_AFSR_ERR 0x02000000 /* Error summary bit */
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#define VMEBUS_AFSR_S 0x01000000 /* MVME error in supervisor space */
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#define VMEBUS_AFSR_ME 0x00800000 /* Multiple error */
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#define VMEBUS_AFSR_RSVD 0x007fffff /* reserved */
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#define VMEBUS_AFSR_BITS "\177\020" \
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"b\27ME\0b\30S\0b\31ERR\0b\32WB\0\33TO\0f\34\3SZ\0"
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struct vmebusvec {
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volatile u_int8_t vmebusvec[16];
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};
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/*
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* VME IO-cache definitions.
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*/
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#define VME_IOC_SIZE 0x8000
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#define VME_IOC_LINESHFT 5
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#define VME_IOC_LINESZ (1 << VME_IOC_LINESHFT)
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/*
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* The VME IO cache lines are selected by bits [13-22] of the DVMA address.
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* A byte within a cache line is selected by bits [0-4]. The bits in between
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* (e.g. [5-12]) are used as the cache tag.
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*/
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#define VME_IOC_IDXSHFT 13
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#define VME_IOC_IDXMASK 0x3ff
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#define VME_IOC_PAGESZ (1 << VME_IOC_IDXSHFT) /* 8192 */
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#define VME_IOC_LINE_IDX(addr) \
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((((u_long)(addr)) >> VME_IOC_IDXSHFT) & VME_IOC_IDXMASK)
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#define VME_IOC_LINE(addr) (VME_IOC_LINE_IDX(addr) << VME_IOC_LINESHFT)
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/* Format of a IO cache tag entry */
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#define VME_IOC_W 0x00100000 /* Allow writes */
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#define VME_IOC_IC 0x00200000 /* Line is cacheable */
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#define VME_IOC_M 0x00400000 /* Line is modified */
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#define VME_IOC_V 0x00800000 /* Data is valid */
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#define VME_IOC_TAGMASK 0xff000000 /* Tag (bits <5-12> of DVMA) */
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#define VME_IOC_BITS "\177\020" \
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"b\24W\0b\25IC\0b\26M\0b\27V\0f\30\10TAG\0"
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/*
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* Physical IO-cache addresses.
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* (expressed as offsets relative to VME vector registers, for want
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* of something better).
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*/
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#define VME_IOC_TAGOFFSET 0x0f000000
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#define VME_IOC_DATAOFFSET 0x0f008000
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#define VME_IOC_FLUSHOFFSET 0x0f020000
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