177 lines
7.1 KiB
C
177 lines
7.1 KiB
C
/* $NetBSD: wdcvar.h,v 1.6 1998/10/12 16:09:18 bouyer Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define WAITTIME (10 * hz) /* time to wait for a completion */
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/* this is a lot for hard drives, but not for cdroms */
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struct channel_queue { /* per channel queue (may be shared) */
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TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer;
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};
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struct channel_softc { /* Per channel data */
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/* Our location */
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int channel;
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/* Our controller's softc */
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struct wdc_softc *wdc;
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/* Our registers */
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bus_space_tag_t cmd_iot;
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bus_space_handle_t cmd_ioh;
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bus_space_tag_t ctl_iot;
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bus_space_handle_t ctl_ioh;
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/* data32{iot,ioh} are only used for 32 bit xfers */
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bus_space_tag_t data32iot;
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bus_space_handle_t data32ioh;
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/* Our state */
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int ch_flags;
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#define WDCF_ACTIVE 0x01 /* channel is active */
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#define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */
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u_int8_t ch_status; /* copy of status register */
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u_int8_t ch_error; /* copy of error register */
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/* per-drive infos */
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struct ata_drive_datas ch_drive[2];
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/*
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* channel queues. May be the same for all channels, if hw channels
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* are not independants
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*/
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struct channel_queue *ch_queue;
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};
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struct wdc_softc { /* Per controller state */
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struct device sc_dev;
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/* mandatory fields */
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int cap;
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/* Capabilities supported by the controller */
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#define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */
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#define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */
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#define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */
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#define WDC_CAPABILITY_DMA 0x0008 /* DMA */
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#define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */
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#define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */
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#define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */
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#define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */
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#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
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u_int8_t pio_mode; /* highest PIO mode supported */
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u_int8_t dma_mode; /* highest DMA mode supported */
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int nchannels; /* Number of channels on this controller */
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struct channel_softc *channels; /* channels-specific datas (array) */
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/* if WDC_CAPABILITY_DMA set in 'cap' */
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void *dma_arg;
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int (*dma_init) __P((void *, int, int, void *, size_t,
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int));
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void (*dma_start) __P((void *, int, int, int));
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int (*dma_finish) __P((void *, int, int, int));
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/* flags passed to DMA functions */
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#define WDC_DMA_READ 0x01
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#define WDC_DMA_POLL 0x02
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/* if WDC_CAPABILITY_HWLOCK set in 'cap' */
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int (*claim_hw) __P((void *, int));
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void (*free_hw) __P((void *));
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};
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/*
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* Description of a command to be handled by a controller.
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* These commands are queued in a list.
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*/
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struct wdc_xfer {
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volatile u_int c_flags;
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#define C_INUSE 0x0001 /* xfer struct is in use */
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#define C_ATAPI 0x0002 /* xfer is ATAPI request */
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#define C_TIMEOU 0x0004 /* xfer processing timed out */
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#define C_NEEDDONE 0x0010 /* need to call upper-level done */
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#define C_POLL 0x0020 /* cmd is polled */
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#define C_DMA 0x0040 /* cmd uses DMA */
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/* Information about our location */
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u_int8_t drive;
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u_int8_t channel;
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/* Information about the current transfer */
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void *cmd; /* wdc, ata or scsipi command structure */
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void *databuf;
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int c_bcount; /* byte count left */
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int c_skip; /* bytes already transferred */
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TAILQ_ENTRY(wdc_xfer) c_xferchain;
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LIST_ENTRY(wdc_xfer) free_list;
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void (*c_start) __P((struct channel_softc *, struct wdc_xfer *));
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int (*c_intr) __P((struct channel_softc *, struct wdc_xfer *));
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};
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/*
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* Public functions which can be called by ATA or ATAPI specific parts,
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* or bus-specific backends.
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*/
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int wdcprobe __P((struct channel_softc *));
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void wdcattach __P((struct channel_softc *));
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int wdcintr __P((void *));
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void wdc_exec_xfer __P((struct channel_softc *, struct wdc_xfer *));
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struct wdc_xfer *wdc_get_xfer __P((int)); /* int = WDC_NOSLEEP/CANSLEEP */
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#define WDC_CANSLEEP 0x00
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#define WDC_NOSLEEP 0x01
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void wdc_free_xfer __P((struct channel_softc *, struct wdc_xfer *));
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void wdcstart __P((struct wdc_softc *, int));
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void wdcrestart __P((void*));
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int wdcreset __P((struct channel_softc *, int));
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#define VERBOSE 1
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#define SILENT 0 /* wdcreset will not print errors */
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int wdcwait __P((struct channel_softc *, int, int, int));
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void wdcbit_bucket __P(( struct channel_softc *, int));
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void wdccommand __P((struct channel_softc *, u_int8_t, u_int8_t, u_int16_t,
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u_int8_t, u_int8_t, u_int8_t, u_int8_t));
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void wdccommandshort __P((struct channel_softc *, int, int));
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void wdctimeout __P((void *arg));
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/*
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* ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
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* command is aborted.
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*/
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#define wait_for_drq(chp, timeout) wdcwait((chp), \
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WDCS_DRDY | WDCS_DSC | WDCS_DRQ, \
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WDCS_DRDY | WDCS_DSC | WDCS_DRQ, (timeout))
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#define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout))
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#define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY | WDCS_DSC, \
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WDCS_DRDY | WDCS_DSC, (timeout))
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/* ATA/ATAPI specs says a device can take 31s to reset */
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#define WDC_RESET_WAIT 31000
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void wdc_atapibus_attach __P((struct channel_softc *));
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int atapi_print __P((void *, const char *));
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