a7533e4cdc
the idle loop. They seem to have gone AWOL sometime in the past. Fixes port-arm/23390. - While here, tidy up the idle loop. - Add a cheap DIAGNOSTIC check for run queue sanity.
1049 lines
26 KiB
ArmAsm
1049 lines
26 KiB
ArmAsm
/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */
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/*
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* Copyright 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* cpuswitch.S
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*
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* cpu switching functions
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*
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* Created : 15/10/94
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*/
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#include "opt_armfpe.h"
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#include "opt_arm32_pmap.h"
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#include "opt_multiprocessor.h"
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#include "opt_lockdebug.h"
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#include "assym.h"
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#include <machine/param.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <machine/asm.h>
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/* LINTSTUB: include <sys/param.h> */
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#undef IRQdisable
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#undef IRQenable
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/*
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* New experimental definitions of IRQdisable and IRQenable
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* These keep FIQ's enabled since FIQ's are special.
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*/
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#define IRQdisable \
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mrs r14, cpsr ; \
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orr r14, r14, #(I32_bit) ; \
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msr cpsr_c, r14 ; \
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#define IRQenable \
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mrs r14, cpsr ; \
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bic r14, r14, #(I32_bit) ; \
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msr cpsr_c, r14 ; \
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/*
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* These are used for switching the translation table/DACR.
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* Since the vector page can be invalid for a short time, we must
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* disable both regular IRQs *and* FIQs.
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*
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* XXX: This is not necessary if the vector table is relocated.
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*/
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#define IRQdisableALL \
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mrs r14, cpsr ; \
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orr r14, r14, #(I32_bit | F32_bit) ; \
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msr cpsr_c, r14
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#define IRQenableALL \
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mrs r14, cpsr ; \
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bic r14, r14, #(I32_bit | F32_bit) ; \
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msr cpsr_c, r14
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.text
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.Lwhichqs:
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.word _C_LABEL(sched_whichqs)
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.Lqs:
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.word _C_LABEL(sched_qs)
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/*
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* cpuswitch()
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*
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* preforms a process context switch.
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* This function has several entry points
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*/
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#ifdef MULTIPROCESSOR
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.Lcpu_info_store:
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.word _C_LABEL(cpu_info_store)
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.Lcurlwp:
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/* FIXME: This is bogus in the general case. */
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.word _C_LABEL(cpu_info_store) + CI_CURLWP
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.Lcurpcb:
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.word _C_LABEL(cpu_info_store) + CI_CURPCB
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#else
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.Lcurlwp:
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.word _C_LABEL(curlwp)
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.Lcurpcb:
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.word _C_LABEL(curpcb)
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#endif
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.Lwant_resched:
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.word _C_LABEL(want_resched)
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.Lcpufuncs:
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.word _C_LABEL(cpufuncs)
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#ifndef MULTIPROCESSOR
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.data
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.global _C_LABEL(curpcb)
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_C_LABEL(curpcb):
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.word 0x00000000
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.text
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#endif
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.Lblock_userspace_access:
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.word _C_LABEL(block_userspace_access)
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.Lcpu_do_powersave:
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.word _C_LABEL(cpu_do_powersave)
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.Lpmap_kernel_cstate:
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.word (kernel_pmap_store + PMAP_CSTATE)
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.Llast_cache_state_ptr:
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.word _C_LABEL(pmap_cache_state)
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/*
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* Idle loop, exercised while waiting for a process to wake up.
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*
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* NOTE: When we jump back to .Lswitch_search, we must have a
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* pointer to whichqs in r7, which is what it is when we arrive
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* here.
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*/
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/* LINTSTUB: Ignore */
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ASENTRY_NP(idle)
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ldr r6, .Lcpu_do_powersave
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IRQenable /* Enable interrupts */
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ldr r6, [r6] /* r6 = cpu_do_powersave */
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#if defined(MULTIPROCESSOR) || defined(LOCKDEBUG)
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bl _C_LABEL(sched_unlock_idle)
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#endif
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/* Drop to spl0 (returns the current spl level in r0). */
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#ifdef __NEWINTR
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mov r0, #(IPL_NONE)
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bl _C_LABEL(_spllower)
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#else /* ! __NEWINTR */
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mov r0, #(_SPL_0)
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bl _C_LABEL(splx)
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#endif /* __NEWINTR */
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teq r6, #0 /* cpu_do_powersave non zero? */
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ldrne r6, .Lcpufuncs
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mov r4, r0 /* Old interrupt level to r4 */
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ldrne r6, [r6, #(CF_SLEEP)]
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/*
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* Main idle loop.
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* r6 points to power-save idle function if required, else NULL.
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*/
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1: ldr r3, [r7] /* r3 = sched_whichqs */
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teq r3, #0
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bne 2f /* We have work to do */
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teq r6, #0 /* Powersave idle? */
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beq 1b /* Nope. Just sit-n-spin. */
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/*
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* Before going into powersave idle mode, disable interrupts
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* and check sched_whichqs one more time.
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*/
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IRQdisableALL
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ldr r3, [r7]
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mov r0, #0
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teq r3, #0 /* sched_whichqs still zero? */
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moveq lr, pc
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moveq pc, r6 /* If so, do powersave idle */
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IRQenableALL
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b 1b /* Back around */
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/*
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* sched_whichqs indicates that at least one lwp is ready to run.
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* Restore the original interrupt priority level, grab the
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* scheduler lock if necessary, and jump back into cpu_switch.
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*/
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2: mov r0, r4
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#if defined(MULTIPROCESSOR) || defined(LOCKDEBUG)
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bl _C_LABEL(splx)
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adr lr, .Lswitch_search
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b _C_LABEL(sched_lock_idle)
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#else
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adr lr, .Lswitch_search
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b _C_LABEL(splx)
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#endif
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/*
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* Find a new lwp to run, save the current context and
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* load the new context
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*
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* Arguments:
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* r0 'struct lwp *' of the current LWP
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*/
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ENTRY(cpu_switch)
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/*
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* Local register usage. Some of these registers are out of date.
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* r1 = oldlwp
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* r2 = spl level
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* r3 = whichqs
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* r4 = queue
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* r5 = &qs[queue]
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* r6 = newlwp
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* r7 = scratch
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*/
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stmfd sp!, {r4-r7, lr}
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/*
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* Indicate that there is no longer a valid process (curlwp = 0).
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* Zero the current PCB pointer while we're at it.
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*/
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ldr r7, .Lcurlwp
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ldr r6, .Lcurpcb
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mov r2, #0x00000000
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str r2, [r7] /* curproc = NULL */
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str r2, [r6] /* curpcb = NULL */
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/* stash the old proc while we call functions */
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mov r5, r0
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/* First phase : find a new lwp */
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ldr r7, .Lwhichqs
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/* rem: r5 = old lwp */
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/* rem: r7 = &whichqs */
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.Lswitch_search:
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IRQdisable
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/* Do we have any active queues */
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ldr r3, [r7]
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/* If not we must idle until we do. */
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teq r3, #0x00000000
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beq _ASM_LABEL(idle)
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/* put old proc back in r1 */
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mov r1, r5
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/* rem: r1 = old lwp */
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/* rem: r3 = whichqs */
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/* rem: interrupts are disabled */
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/* used further down, saves SA stall */
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ldr r6, .Lqs
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/*
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* We have found an active queue. Currently we do not know which queue
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* is active just that one of them is.
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*/
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/* Non-Xscale version of the ffs algorithm devised by d.seal and
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* posted to comp.sys.arm on 16 Feb 1994.
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*/
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rsb r5, r3, #0
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ands r0, r3, r5
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#ifndef __XSCALE__
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adr r5, .Lcpu_switch_ffs_table
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/* X = R0 */
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orr r4, r0, r0, lsl #4 /* r4 = X * 0x11 */
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orr r4, r4, r4, lsl #6 /* r4 = X * 0x451 */
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rsb r4, r4, r4, lsl #16 /* r4 = X * 0x0450fbaf */
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/* now lookup in table indexed on top 6 bits of a4 */
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ldrb r4, [ r5, r4, lsr #26 ]
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#else /* __XSCALE__ */
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clz r4, r0
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rsb r4, r4, #31
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#endif /* __XSCALE__ */
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/* rem: r0 = bit mask of chosen queue (1 << r4) */
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/* rem: r1 = old lwp */
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/* rem: r3 = whichqs */
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/* rem: r4 = queue number */
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/* rem: interrupts are disabled */
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/* Get the address of the queue (&qs[queue]) */
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add r5, r6, r4, lsl #3
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/*
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* Get the lwp from the queue and place the next process in
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* the queue at the head. This basically unlinks the lwp at
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* the head of the queue.
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*/
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ldr r6, [r5, #(L_FORW)]
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#ifdef DIAGNOSTIC
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cmp r6, r5
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beq .Lswitch_bogons
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#endif
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/* rem: r6 = new lwp */
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ldr r7, [r6, #(L_FORW)]
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str r7, [r5, #(L_FORW)]
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/*
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* Test to see if the queue is now empty. If the head of the queue
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* points to the queue itself then there are no more lwps in
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* the queue. We can therefore clear the queue not empty flag held
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* in r3.
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*/
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teq r5, r7
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biceq r3, r3, r0
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/* rem: r0 = bit mask of chosen queue (1 << r4) - NOT NEEDED AN MORE */
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/* Fix the back pointer for the lwp now at the head of the queue. */
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ldr r0, [r6, #(L_BACK)]
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str r0, [r7, #(L_BACK)]
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/* Update the RAM copy of the queue not empty flags word. */
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ldreq r7, .Lwhichqs
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streq r3, [r7]
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/* rem: r1 = old lwp */
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/* rem: r3 = whichqs - NOT NEEDED ANY MORE */
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/* rem: r4 = queue number - NOT NEEDED ANY MORE */
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/* rem: r6 = new lwp */
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/* rem: interrupts are disabled */
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/* Clear the want_resched flag */
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ldr r7, .Lwant_resched
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mov r0, #0x00000000
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str r0, [r7]
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/*
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* Clear the back pointer of the lwp we have removed from
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* the head of the queue. The new lwp is isolated now.
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*/
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str r0, [r6, #(L_BACK)]
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#if defined(MULTIPROCESSOR) || defined(LOCKDEBUG)
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/*
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* unlock the sched_lock, but leave interrupts off, for now.
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*/
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mov r7, r1
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bl _C_LABEL(sched_unlock_idle)
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mov r1, r7
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#endif
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.Lswitch_resume:
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/* rem: r1 = old lwp */
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/* rem: r4 = return value [not used if came from cpu_switchto()] */
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/* rem: r6 = new process */
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/* rem: interrupts are disabled */
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#ifdef MULTIPROCESSOR
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/* XXX use curcpu() */
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ldr r0, .Lcpu_info_store
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str r0, [r6, #(L_CPU)]
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#else
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/* l->l_cpu initialized in fork1() for single-processor */
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#endif
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/* Process is now on a processor. */
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mov r0, #LSONPROC /* l->l_stat = LSONPROC */
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str r0, [r6, #(L_STAT)]
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/* We have a new curlwp now so make a note it */
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ldr r7, .Lcurlwp
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str r6, [r7]
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|
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/* Hook in a new pcb */
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ldr r7, .Lcurpcb
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ldr r0, [r6, #(L_ADDR)]
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str r0, [r7]
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/* At this point we can allow IRQ's again. */
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IRQenable
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/* rem: r1 = old lwp */
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/* rem: r4 = return value */
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/* rem: r6 = new process */
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/* rem: interrupts are enabled */
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|
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/*
|
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* If the new process is the same as the process that called
|
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* cpu_switch() then we do not need to save and restore any
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* contexts. This means we can make a quick exit.
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* The test is simple if curlwp on entry (now in r1) is the
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* same as the proc removed from the queue we can jump to the exit.
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*/
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teq r1, r6
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moveq r4, #0x00000000 /* default to "didn't switch" */
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beq .Lswitch_return
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|
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/*
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* At this point, we are guaranteed to be switching to
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* a new lwp.
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*/
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mov r4, #0x00000001
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|
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/* Remember the old lwp in r0 */
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mov r0, r1
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|
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/*
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* If the old lwp on entry to cpu_switch was zero then the
|
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* process that called it was exiting. This means that we do
|
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* not need to save the current context. Instead we can jump
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* straight to restoring the context for the new process.
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|
*/
|
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teq r0, #0x00000000
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beq .Lswitch_exited
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|
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/* rem: r0 = old lwp */
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/* rem: r4 = return value */
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/* rem: r6 = new process */
|
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/* rem: interrupts are enabled */
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|
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/* Stage two : Save old context */
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|
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/* Get the user structure for the old lwp. */
|
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ldr r1, [r0, #(L_ADDR)]
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|
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/* Save all the registers in the old lwp's pcb */
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#ifndef __XSCALE__
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add r7, r1, #(PCB_R8)
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stmia r7, {r8-r13}
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#else
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strd r8, [r1, #(PCB_R8)]
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strd r10, [r1, #(PCB_R10)]
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strd r12, [r1, #(PCB_R12)]
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#endif
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|
|
/*
|
|
* NOTE: We can now use r8-r13 until it is time to restore
|
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* them for the new process.
|
|
*/
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|
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/* Remember the old PCB. */
|
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mov r8, r1
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|
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/* r1 now free! */
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|
|
/* Get the user structure for the new process in r9 */
|
|
ldr r9, [r6, #(L_ADDR)]
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|
|
/*
|
|
* This can be optimised... We know we want to go from SVC32
|
|
* mode to UND32 mode
|
|
*/
|
|
mrs r3, cpsr
|
|
bic r2, r3, #(PSR_MODE)
|
|
orr r2, r2, #(PSR_UND32_MODE | I32_bit)
|
|
msr cpsr_c, r2
|
|
|
|
str sp, [r8, #(PCB_UND_SP)]
|
|
|
|
msr cpsr_c, r3 /* Restore the old mode */
|
|
|
|
/* rem: r0 = old lwp */
|
|
/* rem: r4 = return value */
|
|
/* rem: r6 = new process */
|
|
/* rem: r8 = old PCB */
|
|
/* rem: r9 = new PCB */
|
|
/* rem: interrupts are enabled */
|
|
|
|
/* What else needs to be saved Only FPA stuff when that is supported */
|
|
|
|
/* Third phase : restore saved context */
|
|
|
|
/* rem: r0 = old lwp */
|
|
/* rem: r4 = return value */
|
|
/* rem: r6 = new lwp */
|
|
/* rem: r8 = old PCB */
|
|
/* rem: r9 = new PCB */
|
|
/* rem: interrupts are enabled */
|
|
|
|
/*
|
|
* Get the new L1 table pointer into r11. If we're switching to
|
|
* an LWP with the same address space as the outgoing one, we can
|
|
* skip the cache purge and the TTB load.
|
|
*
|
|
* To avoid data dep stalls that would happen anyway, we try
|
|
* and get some useful work done in the mean time.
|
|
*/
|
|
ldr r10, [r8, #(PCB_PAGEDIR)] /* r10 = old L1 */
|
|
ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
|
|
|
|
ldr r0, [r8, #(PCB_DACR)] /* r0 = old DACR */
|
|
ldr r1, [r9, #(PCB_DACR)] /* r1 = new DACR */
|
|
ldr r8, [r9, #(PCB_CSTATE)] /* r8 = &new_pmap->pm_cstate */
|
|
ldr r5, .Llast_cache_state_ptr /* Previous thread's cstate */
|
|
|
|
teq r10, r11 /* Same L1? */
|
|
ldr r5, [r5]
|
|
cmpeq r0, r1 /* Same DACR? */
|
|
beq .Lcs_context_switched /* yes! */
|
|
|
|
ldr r3, .Lblock_userspace_access
|
|
mov r12, #0
|
|
cmp r5, #0 /* No last vm? (switch_exit) */
|
|
beq .Lcs_cache_purge_skipped /* No, we can skip cache flsh */
|
|
|
|
mov r2, #DOMAIN_CLIENT
|
|
cmp r1, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
|
|
beq .Lcs_cache_purge_skipped /* Yup. Don't flush cache */
|
|
|
|
cmp r5, r8 /* Same userland VM space? */
|
|
ldrneb r12, [r5, #(CS_CACHE_ID)] /* Last VM space cache state */
|
|
|
|
/*
|
|
* We're definately switching to a new userland VM space,
|
|
* and the previous userland VM space has yet to be flushed
|
|
* from the cache/tlb.
|
|
*
|
|
* r12 holds the previous VM space's cs_cache_id state
|
|
*/
|
|
tst r12, #0xff /* Test cs_cache_id */
|
|
beq .Lcs_cache_purge_skipped /* VM space is not in cache */
|
|
|
|
/*
|
|
* Definately need to flush the cache.
|
|
* Mark the old VM space as NOT being resident in the cache.
|
|
*/
|
|
mov r2, #0x00000000
|
|
strb r2, [r5, #(CS_CACHE_ID)]
|
|
strb r2, [r5, #(CS_CACHE_D)]
|
|
|
|
/*
|
|
* Don't allow user space access between the purge and the switch.
|
|
*/
|
|
mov r2, #0x00000001
|
|
str r2, [r3]
|
|
|
|
stmfd sp!, {r0-r3}
|
|
ldr r1, .Lcpufuncs
|
|
mov lr, pc
|
|
ldr pc, [r1, #CF_IDCACHE_WBINV_ALL]
|
|
ldmfd sp!, {r0-r3}
|
|
|
|
.Lcs_cache_purge_skipped:
|
|
/* rem: r1 = new DACR */
|
|
/* rem: r3 = &block_userspace_access */
|
|
/* rem: r4 = return value */
|
|
/* rem: r5 = &old_pmap->pm_cstate (or NULL) */
|
|
/* rem: r6 = new lwp */
|
|
/* rem: r8 = &new_pmap->pm_cstate */
|
|
/* rem: r9 = new PCB */
|
|
/* rem: r10 = old L1 */
|
|
/* rem: r11 = new L1 */
|
|
|
|
mov r2, #0x00000000
|
|
ldr r7, [r9, #(PCB_PL1VEC)]
|
|
|
|
/*
|
|
* At this point we need to kill IRQ's again.
|
|
*
|
|
* XXXSCW: Don't need to block FIQs if vectors have been relocated
|
|
*/
|
|
IRQdisableALL
|
|
|
|
/*
|
|
* Interrupts are disabled so we can allow user space accesses again
|
|
* as none will occur until interrupts are re-enabled after the
|
|
* switch.
|
|
*/
|
|
str r2, [r3]
|
|
|
|
/*
|
|
* Ensure the vector table is accessible by fixing up the L1
|
|
*/
|
|
cmp r7, #0 /* No need to fixup vector table? */
|
|
ldrne r2, [r7] /* But if yes, fetch current value */
|
|
ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */
|
|
mcr p15, 0, r1, c3, c0, 0 /* Update DACR for new context */
|
|
cmpne r2, r0 /* Stuffing the same value? */
|
|
#ifndef PMAP_INCLUDE_PTE_SYNC
|
|
strne r0, [r7] /* Nope, update it */
|
|
#else
|
|
beq .Lcs_same_vector
|
|
str r0, [r7] /* Otherwise, update it */
|
|
|
|
/*
|
|
* Need to sync the cache to make sure that last store is
|
|
* visible to the MMU.
|
|
*/
|
|
ldr r2, .Lcpufuncs
|
|
mov r0, r7
|
|
mov r1, #4
|
|
mov lr, pc
|
|
ldr pc, [r2, #CF_DCACHE_WB_RANGE]
|
|
|
|
.Lcs_same_vector:
|
|
#endif /* PMAP_INCLUDE_PTE_SYNC */
|
|
|
|
cmp r10, r11 /* Switching to the same L1? */
|
|
ldr r10, .Lcpufuncs
|
|
beq .Lcs_same_l1 /* Yup. */
|
|
|
|
/*
|
|
* Do a full context switch, including full TLB flush.
|
|
*/
|
|
mov r0, r11
|
|
mov lr, pc
|
|
ldr pc, [r10, #CF_CONTEXT_SWITCH]
|
|
|
|
/*
|
|
* Mark the old VM space as NOT being resident in the TLB
|
|
*/
|
|
mov r2, #0x00000000
|
|
cmp r5, #0
|
|
strneh r2, [r5, #(CS_TLB_ID)]
|
|
b .Lcs_context_switched
|
|
|
|
/*
|
|
* We're switching to a different process in the same L1.
|
|
* In this situation, we only need to flush the TLB for the
|
|
* vector_page mapping, and even then only if r7 is non-NULL.
|
|
*/
|
|
.Lcs_same_l1:
|
|
cmp r7, #0
|
|
movne r0, #0 /* We *know* vector_page's VA is 0x0 */
|
|
movne lr, pc
|
|
ldrne pc, [r10, #CF_TLB_FLUSHID_SE]
|
|
|
|
.Lcs_context_switched:
|
|
/* rem: r8 = &new_pmap->pm_cstate */
|
|
|
|
/* XXXSCW: Safe to re-enable FIQs here */
|
|
|
|
/*
|
|
* The new VM space is live in the cache and TLB.
|
|
* Update its cache/tlb state, and if it's not the kernel
|
|
* pmap, update the 'last cache state' pointer.
|
|
*/
|
|
mov r2, #-1
|
|
ldr r5, .Lpmap_kernel_cstate
|
|
ldr r0, .Llast_cache_state_ptr
|
|
str r2, [r8, #(CS_ALL)]
|
|
cmp r5, r8
|
|
strne r8, [r0]
|
|
|
|
/* rem: r4 = return value */
|
|
/* rem: r6 = new lwp */
|
|
/* rem: r9 = new PCB */
|
|
|
|
/*
|
|
* This can be optimised... We know we want to go from SVC32
|
|
* mode to UND32 mode
|
|
*/
|
|
mrs r3, cpsr
|
|
bic r2, r3, #(PSR_MODE)
|
|
orr r2, r2, #(PSR_UND32_MODE)
|
|
msr cpsr_c, r2
|
|
|
|
ldr sp, [r9, #(PCB_UND_SP)]
|
|
|
|
msr cpsr_c, r3 /* Restore the old mode */
|
|
|
|
/* Restore all the save registers */
|
|
#ifndef __XSCALE__
|
|
add r7, r9, #PCB_R8
|
|
ldmia r7, {r8-r13}
|
|
|
|
sub r7, r7, #PCB_R8 /* restore PCB pointer */
|
|
#else
|
|
mov r7, r9
|
|
ldr r8, [r7, #(PCB_R8)]
|
|
ldr r9, [r7, #(PCB_R9)]
|
|
ldr r10, [r7, #(PCB_R10)]
|
|
ldr r11, [r7, #(PCB_R11)]
|
|
ldr r12, [r7, #(PCB_R12)]
|
|
ldr r13, [r7, #(PCB_SP)]
|
|
#endif
|
|
|
|
ldr r5, [r6, #(L_PROC)] /* fetch the proc for below */
|
|
|
|
/* rem: r4 = return value */
|
|
/* rem: r5 = new lwp's proc */
|
|
/* rem: r6 = new lwp */
|
|
/* rem: r7 = new pcb */
|
|
|
|
#ifdef ARMFPE
|
|
add r0, r7, #(USER_SIZE) & 0x00ff
|
|
add r0, r0, #(USER_SIZE) & 0xff00
|
|
bl _C_LABEL(arm_fpe_core_changecontext)
|
|
#endif
|
|
|
|
/* We can enable interrupts again */
|
|
IRQenableALL
|
|
|
|
/* rem: r4 = return value */
|
|
/* rem: r5 = new lwp's proc */
|
|
/* rem: r6 = new lwp */
|
|
/* rem: r7 = new PCB */
|
|
|
|
/*
|
|
* Check for restartable atomic sequences (RAS).
|
|
*/
|
|
|
|
ldr r2, [r5, #(P_RASLIST)]
|
|
ldr r1, [r7, #(PCB_TF)] /* r1 = trapframe (used below) */
|
|
teq r2, #0 /* p->p_nras == 0? */
|
|
bne .Lswitch_do_ras /* no, check for one */
|
|
|
|
.Lswitch_return:
|
|
/* cpu_switch returns 1 == switched, 0 == didn't switch */
|
|
mov r0, r4
|
|
|
|
/*
|
|
* Pull the registers that got pushed when either savectx() or
|
|
* cpu_switch() was called and return.
|
|
*/
|
|
ldmfd sp!, {r4-r7, pc}
|
|
|
|
.Lswitch_do_ras:
|
|
ldr r1, [r1, #(TF_PC)] /* second ras_lookup() arg */
|
|
mov r0, r5 /* first ras_lookup() arg */
|
|
bl _C_LABEL(ras_lookup)
|
|
cmn r0, #1 /* -1 means "not in a RAS" */
|
|
ldrne r1, [r7, #(PCB_TF)]
|
|
strne r0, [r1, #(TF_PC)]
|
|
b .Lswitch_return
|
|
|
|
.Lswitch_exited:
|
|
/*
|
|
* We skip the cache purge because switch_exit() already did it.
|
|
* Load up registers the way .Lcs_cache_purge_skipped expects.
|
|
* Userpsace access already blocked by switch_exit().
|
|
*/
|
|
ldr r9, [r6, #(L_ADDR)] /* r9 = new PCB */
|
|
ldr r3, .Lblock_userspace_access
|
|
mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
|
|
mov r5, #0 /* No previous cache state */
|
|
ldr r1, [r9, #(PCB_DACR)] /* r1 = new DACR */
|
|
ldr r8, [r9, #(PCB_CSTATE)] /* r8 = new cache state */
|
|
ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
|
|
b .Lcs_cache_purge_skipped
|
|
|
|
|
|
#ifdef DIAGNOSTIC
|
|
.Lswitch_bogons:
|
|
adr r0, .Lswitch_panic_str
|
|
bl _C_LABEL(panic)
|
|
1: nop
|
|
b 1b
|
|
|
|
.Lswitch_panic_str:
|
|
.asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n"
|
|
#endif
|
|
|
|
/*
|
|
* cpu_switchto(struct lwp *current, struct lwp *next)
|
|
* Switch to the specified next LWP
|
|
* Arguments:
|
|
*
|
|
* r0 'struct lwp *' of the current LWP
|
|
* r1 'struct lwp *' of the LWP to switch to
|
|
*/
|
|
ENTRY(cpu_switchto)
|
|
stmfd sp!, {r4-r7, lr}
|
|
|
|
mov r6, r1 /* save new lwp */
|
|
|
|
#if defined(LOCKDEBUG)
|
|
mov r5, r0 /* save old lwp */
|
|
bl _C_LABEL(sched_unlock_idle)
|
|
mov r1, r5
|
|
#else
|
|
mov r1, r0
|
|
#endif
|
|
|
|
IRQdisable
|
|
|
|
/*
|
|
* Okay, set up registers the way cpu_switch() wants them,
|
|
* and jump into the middle of it (where we bring up the
|
|
* new process).
|
|
*
|
|
* r1 = old lwp (r6 = new lwp)
|
|
*/
|
|
b .Lswitch_resume
|
|
|
|
/*
|
|
* void switch_exit(struct lwp *l, struct lwp *l0, void (*exit)(struct lwp *));
|
|
* Switch to lwp0's saved context and deallocate the address space and kernel
|
|
* stack for l. Then jump into cpu_switch(), as if we were in lwp0 all along.
|
|
*/
|
|
|
|
/* LINTSTUB: Func: void switch_exit(struct lwp *l, struct lwp *l0, void (*func)(struct lwp *)) */
|
|
ENTRY(switch_exit)
|
|
/*
|
|
* The process is going away, so we can use callee-saved
|
|
* registers here without having to save them.
|
|
*/
|
|
|
|
mov r4, r0
|
|
ldr r0, .Lcurlwp
|
|
|
|
mov r5, r1
|
|
ldr r1, .Lblock_userspace_access
|
|
|
|
mov r6, r2
|
|
|
|
/*
|
|
* r4 = lwp
|
|
* r5 = lwp0
|
|
* r6 = exit func
|
|
*/
|
|
|
|
mov r2, #0x00000000 /* curlwp = NULL */
|
|
str r2, [r0]
|
|
|
|
/*
|
|
* We're about to clear both the cache and the TLB.
|
|
* Make sure to zap the 'last cache state' pointer since the
|
|
* pmap might be about to go away. Also ensure the outgoing
|
|
* VM space's cache state is marked as NOT resident in the
|
|
* cache, and that lwp0's cache state IS resident.
|
|
*/
|
|
ldr r7, [r4, #(L_ADDR)] /* r7 = old lwp's PCB */
|
|
ldr r0, .Llast_cache_state_ptr /* Last userland cache state */
|
|
ldr r9, [r7, #(PCB_CSTATE)] /* Fetch cache state pointer */
|
|
ldr r3, [r5, #(L_ADDR)] /* r3 = lwp0's PCB */
|
|
str r2, [r0] /* No previous cache state */
|
|
str r2, [r9, #(CS_ALL)] /* Zap old lwp's cache state */
|
|
ldr r3, [r3, #(PCB_CSTATE)] /* lwp0's cache state */
|
|
mov r2, #-1
|
|
str r2, [r3, #(CS_ALL)] /* lwp0 is in da cache! */
|
|
|
|
/*
|
|
* Don't allow user space access between the purge and the switch.
|
|
*/
|
|
mov r2, #0x00000001
|
|
str r2, [r1]
|
|
|
|
/* Switch to lwp0 context */
|
|
|
|
ldr r9, .Lcpufuncs
|
|
mov lr, pc
|
|
ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
|
|
|
|
ldr r0, [r7, #(PCB_PL1VEC)]
|
|
ldr r1, [r7, #(PCB_DACR)]
|
|
|
|
/*
|
|
* r0 = Pointer to L1 slot for vector_page (or NULL)
|
|
* r1 = lwp0's DACR
|
|
* r4 = lwp we're switching from
|
|
* r5 = lwp0
|
|
* r6 = exit func
|
|
* r7 = lwp0's PCB
|
|
* r9 = cpufuncs
|
|
*/
|
|
|
|
IRQdisableALL
|
|
|
|
/*
|
|
* Ensure the vector table is accessible by fixing up lwp0's L1
|
|
*/
|
|
cmp r0, #0 /* No need to fixup vector table? */
|
|
ldrne r3, [r0] /* But if yes, fetch current value */
|
|
ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */
|
|
mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */
|
|
cmpne r3, r2 /* Stuffing the same value? */
|
|
strne r2, [r0] /* Store if not. */
|
|
|
|
#ifdef PMAP_INCLUDE_PTE_SYNC
|
|
/*
|
|
* Need to sync the cache to make sure that last store is
|
|
* visible to the MMU.
|
|
*/
|
|
movne r1, #4
|
|
movne lr, pc
|
|
ldrne pc, [r9, #CF_DCACHE_WB_RANGE]
|
|
#endif /* PMAP_INCLUDE_PTE_SYNC */
|
|
|
|
/*
|
|
* Note: We don't do the same optimisation as cpu_switch() with
|
|
* respect to avoiding flushing the TLB if we're switching to
|
|
* the same L1 since this process' VM space may be about to go
|
|
* away, so we don't want *any* turds left in the TLB.
|
|
*/
|
|
|
|
/* Switch the memory to the new process */
|
|
ldr r0, [r7, #(PCB_PAGEDIR)]
|
|
mov lr, pc
|
|
ldr pc, [r9, #CF_CONTEXT_SWITCH]
|
|
|
|
ldr r0, .Lcurpcb
|
|
|
|
/* Restore all the save registers */
|
|
#ifndef __XSCALE__
|
|
add r1, r7, #PCB_R8
|
|
ldmia r1, {r8-r13}
|
|
#else
|
|
ldr r8, [r7, #(PCB_R8)]
|
|
ldr r9, [r7, #(PCB_R9)]
|
|
ldr r10, [r7, #(PCB_R10)]
|
|
ldr r11, [r7, #(PCB_R11)]
|
|
ldr r12, [r7, #(PCB_R12)]
|
|
ldr r13, [r7, #(PCB_SP)]
|
|
#endif
|
|
str r7, [r0] /* curpcb = lwp0's PCB */
|
|
|
|
IRQenableALL
|
|
|
|
/*
|
|
* Schedule the vmspace and stack to be freed.
|
|
*/
|
|
mov r0, r4 /* {lwp_}exit2(l) */
|
|
mov lr, pc
|
|
mov pc, r6
|
|
|
|
#if defined(MULTIPROCESSOR) || defined(LOCKDEBUG)
|
|
bl _C_LABEL(sched_lock_idle)
|
|
#endif
|
|
|
|
ldr r7, .Lwhichqs /* r7 = &whichqs */
|
|
mov r5, #0x00000000 /* r5 = old lwp = NULL */
|
|
b .Lswitch_search
|
|
|
|
/* LINTSTUB: Func: void savectx(struct pcb *pcb) */
|
|
ENTRY(savectx)
|
|
/*
|
|
* r0 = pcb
|
|
*/
|
|
|
|
/* Push registers.*/
|
|
stmfd sp!, {r4-r7, lr}
|
|
|
|
/* Store all the registers in the process's pcb */
|
|
#ifndef __XSCALE__
|
|
add r2, r0, #(PCB_R8)
|
|
stmia r2, {r8-r13}
|
|
#else
|
|
strd r8, [r0, #(PCB_R8)]
|
|
strd r10, [r0, #(PCB_R10)]
|
|
strd r12, [r0, #(PCB_R12)]
|
|
#endif
|
|
|
|
/* Pull the regs of the stack */
|
|
ldmfd sp!, {r4-r7, pc}
|
|
|
|
ENTRY(proc_trampoline)
|
|
#ifdef __NEWINTR
|
|
mov r0, #(IPL_NONE)
|
|
bl _C_LABEL(_spllower)
|
|
#else /* ! __NEWINTR */
|
|
mov r0, #(_SPL_0)
|
|
bl _C_LABEL(splx)
|
|
#endif /* __NEWINTR */
|
|
|
|
#ifdef MULTIPROCESSOR
|
|
bl _C_LABEL(proc_trampoline_mp)
|
|
#endif
|
|
mov r0, r5
|
|
mov r1, sp
|
|
mov lr, pc
|
|
mov pc, r4
|
|
|
|
/* Kill irq's */
|
|
mrs r0, cpsr
|
|
orr r0, r0, #(I32_bit)
|
|
msr cpsr_c, r0
|
|
|
|
PULLFRAME
|
|
|
|
movs pc, lr /* Exit */
|
|
|
|
#ifndef __XSCALE__
|
|
.type .Lcpu_switch_ffs_table, _ASM_TYPE_OBJECT;
|
|
.Lcpu_switch_ffs_table:
|
|
/* same as ffs table but all nums are -1 from that */
|
|
/* 0 1 2 3 4 5 6 7 */
|
|
.byte 0, 0, 1, 12, 2, 6, 0, 13 /* 0- 7 */
|
|
.byte 3, 0, 7, 0, 0, 0, 0, 14 /* 8-15 */
|
|
.byte 10, 4, 0, 0, 8, 0, 0, 25 /* 16-23 */
|
|
.byte 0, 0, 0, 0, 0, 21, 27, 15 /* 24-31 */
|
|
.byte 31, 11, 5, 0, 0, 0, 0, 0 /* 32-39 */
|
|
.byte 9, 0, 0, 24, 0, 0, 20, 26 /* 40-47 */
|
|
.byte 30, 0, 0, 0, 0, 23, 0, 19 /* 48-55 */
|
|
.byte 29, 0, 22, 18, 28, 17, 16, 0 /* 56-63 */
|
|
#endif /* !__XSCALE_ */
|