227 lines
6.3 KiB
C
227 lines
6.3 KiB
C
/* $NetBSD: tsreg.h,v 1.2 2000/06/26 02:42:11 thorpej Exp $ */
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/*-
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* Copyright (c) 1999 by Ross Harvey. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ross Harvey.
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* 4. The name of Ross Harvey may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
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* ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* 21272 Core Logic registers and constants.
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*/
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#define tsreg() { Generate ctags(1) key. }
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/*
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* Superpage pointer from physical address.
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*/
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#define S_PAGE(phys) ((void *)ALPHA_PHYS_TO_K0SEG(phys))
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/*
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* {LD,ST}QP: LoaD and STore Quad Physical
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*/
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#define LDQP(a) (*(volatile long *)ALPHA_PHYS_TO_K0SEG(a))
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#define STQP(a) LDQP(a)
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/*
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* Define extraction functions for bit fields via length and left,right bitno
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*/
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#define TSFIELD(r,offs,len) (((r) >> (offs)) & (~0UL >> (64 - (len))))
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#define TSFIELDBB(r,lb,rb) TSFIELD((r), (rb), (lb) - (rb) + 1)
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/*
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* EV6 has a new superpage which can pass through 44 address bits. (Umm, a
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* superduperpage?) But, the firmware doesn't turn it on, so we use the old
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* one and let the HW sign extend va/pa<40> to get us the pa<43> that makes
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* the needed I/O space access. This is just as well; it means we don't have
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* to worry about which GENERIC code might get called on other CPU models.
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*
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* E.g., we want this: 0x0801##a000##0000
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* We use this: 0x0101##a000##0000
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* ...mix in the old SP: 0xffff##fc00##0000##0000
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* ...after PA sign ext: 0xffff##ff00##a000##0000
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* (PA<42:41> ignored)
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*/
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/*
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* This hack allows us to map the I/O address space without using
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* the KSEG sign extention hack.
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*/
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#define TS_PHYSADDR(x) \
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(((x) & ~0x0100##0000##0000) | 0x0800##0000##0000)
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/*
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* Cchip CSR Map
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*/
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#define TS_C_CSC 0x101##a000##0000UL /* Cchip System Configuration */
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# define CSC_P1P (1L << 14)
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# define CSC_BC(r) TSFIELD((r), 0, 2)
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# define CSC_AW (1L << 8)
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#define TS_C_MTR 0x101##a000##0040UL
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#define TS_C_MISC 0x101##a000##0080UL /* Miscellaneous Register */
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# define MISC_REV(r) TSFIELD((r), 39, 8)
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#define TS_C_MPD 0x101##a000##00c0UL
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#define TS_C_AAR0 0x101##a000##0100UL
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#define TS_C_AAR1 0x101##a000##0140UL
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#define TS_C_AAR2 0x101##a000##0180UL
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#define TS_C_AAR3 0x101##a000##01c0UL
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# define AAR_ASIZ(r) TSFIELD((r), 12, 4)
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# define AAR_SPLIT (1L << 8)
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#define TS_C_DIM0 0x101##a000##0200UL
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#define TS_C_DIM1 0x101##a000##0240UL
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#define TS_C_DIR0 0x101##a000##0280UL
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#define TS_C_DIR1 0x101##a000##02c0UL
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#define TS_C_DRIR 0x101##a000##0300UL
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#define TS_C_PRBEN 0x101##a000##0340UL
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#define TS_C_IIC0 0x101##a000##0380UL
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#define TS_C_IIC1 0x101##a000##03c0UL
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#define TS_C_MPR0 0x101##a000##0400UL
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#define TS_C_MPR1 0x101##a000##0440UL
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#define TS_C_MPR2 0x101##a000##0480UL
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#define TS_C_MPR3 0x101##a000##04c0UL
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#define TS_C_MCTL 0x101##a000##0500UL
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#define TS_C_TTR 0x101##a000##0580UL
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#define TS_C_TDR 0x101##a000##05c0UL
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/*
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* Dchip CSR Map
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*/
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#define TS_D_DSC 0x101##b000##0800UL
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#define TS_D_STR 0x101##b000##0840UL
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#define TS_D_DREV 0x101##b000##0880UL
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#define TS_D_DSC2 0x101##b000##08c0UL
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/*
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* Pchip CSR Offsets
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*/
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#define P_WSBA0 0x0000
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#define P_WSBA1 0x0040
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#define P_WSBA2 0x0080
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#define P_WSBA3 0x00c0
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# define WSBA_ADDR(r) (TSFIELDBB((r), 31, 20) << 20)
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# define WSBA_SG 2
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# define WSBA_ENA 1
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#define P_WSM0 0x0100
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#define P_WSM1 0x0140
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#define P_WSM2 0x0180
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#define P_WSM3 0x01c0
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# define WSM_AM(r) TSFIELDBB((r), 31, 20)
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# define WSM_LEN(r) ((WSM_AM(r) + 1) << 20)
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#define P_TBA0 0x0200
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#define P_TBA1 0x0240
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#define P_TBA2 0x0280
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#define P_TBA3 0x02c0
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#define P_PCTL 0x0300
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#define P_PLAT 0x0340
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/* reserved 0x0380 */
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#define P_PERROR 0x03c0
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#define P_PERRMASK 0x0400
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#define P_PERRSET 0x0440
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#define P_TLBIV 0x0480
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#define P_TLBIA 0x04c0
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#define P_PMONCTL 0x0500
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#define P_PMONCNT 0x0540
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#define P_SPRST 0x0800
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#define TS_STEP 0x40
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/*
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* Pchip I/O offsets
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*/
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#define P_CSRBASE 0x001##8000##0000UL
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#define P_PCI_MEM 0
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#define P_PCI_IO 0x001##fc00##0000UL
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#define P_PCI_CONFIG 0x001##fe00##0000UL
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/*
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* Construct EV6 I/O Space Address for Pchip 0 and Pchip 1.
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*/
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#define TS_P0(offs) (0x100##0000##0000UL + (offs))
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#define TS_P1(offs) (0x102##0000##0000UL + (offs))
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#define TS_Pn(n, offs) (0x100##0000##0000UL + 0x2##0000##0000UL * (n) + (offs))
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/*
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* Tsunami Generic Register Type
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*/
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typedef struct _ts_gr {
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volatile u_int64_t tsg_r;
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long tsg_deadspace[7];
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} TS_GR;
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/*
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* Tsunami Pchip
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*/
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struct ts_pchip {
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TS_GR tsp_wsba[4]; /* Window Space Base Address */
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TS_GR tsp_wsm[4]; /* Window Space Mask */
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TS_GR tsp_tba[4]; /* Translated Base Address */
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TS_GR tsp_pctl; /* Pchip Control */
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TS_GR tsp_plat; /* Pchip Latency */
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TS_GR tsp_resA;
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TS_GR tsp_error; /* Pchip Error */
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TS_GR tsp_perrmask; /* Pchip Error Mask */
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TS_GR tsp_perrset; /* Pchip Error Set */
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TS_GR tsp_tlbiv; /* Translation Buffer Invalidate Virtual */
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TS_GR tsp_tlbia; /* Translation Buffer Invalidate All */
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TS_GR tsp_pmonctl; /* PChip Monitor Control */
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TS_GR tsp_pmoncnt; /* PChip Monitor Counters */
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TS_GR tsp_resB;
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TS_GR tsp_resC;
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TS_GR tsp_resD_K[8];
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TS_GR tsp_sprts; /* ??? */
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};
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