474 lines
12 KiB
C
474 lines
12 KiB
C
/* $NetBSD: pcibios.c,v 1.2 1999/11/17 07:33:41 thorpej Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Interface to the PCI BIOS and PCI Interrupt Routing table.
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*/
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#include "opt_pcibios.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <dev/isa/isareg.h>
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#include <machine/isa_machdep.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <i386/pci/pcibios.h>
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#ifdef PCIBIOS_INTR_FIXUP
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#include <i386/pci/pci_intr_fixup.h>
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#endif
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#ifdef PCIBIOS_BUS_FIXUP
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#include <i386/pci/pci_bus_fixup.h>
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#endif
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#include <machine/bios32.h>
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int pcibios_present;
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struct pcibios_pir_header pcibios_pir_header;
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struct pcibios_intr_routing *pcibios_pir_table;
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int pcibios_pir_table_nentries;
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int pcibios_max_bus;
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struct bios32_entry pcibios_entry;
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void pcibios_pir_init __P((void));
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int pcibios_get_status __P((u_int32_t *, u_int32_t *, u_int32_t *,
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u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *));
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int pcibios_get_intr_routing __P((struct pcibios_intr_routing *,
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int *, u_int16_t *));
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int pcibios_return_code __P((u_int16_t, const char *));
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void pcibios_print_exclirq __P((void));
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#ifdef PCIINTR_DEBUG
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void pcibios_print_pir_table __P((void));
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#endif
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#define PCI_IRQ_TABLE_START 0xf0000
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#define PCI_IRQ_TABLE_END 0xfffff
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void
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pcibios_init()
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{
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struct bios32_entry_info ei;
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u_int32_t rev_maj, rev_min, mech1, mech2, scmech1, scmech2;
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if (bios32_service(BIOS32_MAKESIG('$', 'P', 'C', 'I'),
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&pcibios_entry, &ei) == 0) {
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/*
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* No PCI BIOS found; will fall back on old
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* mechanism.
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*/
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return;
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}
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/*
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* We've located the PCI BIOS service; get some information
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* about it.
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*/
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if (pcibios_get_status(&rev_maj, &rev_min, &mech1, &mech2,
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&scmech1, &scmech2, &pcibios_max_bus) != PCIBIOS_SUCCESS) {
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/*
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* We can't use the PCI BIOS; will fall back on old
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* mechanism.
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*/
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return;
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}
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printf("PCI BIOS rev. %d.%d found at 0x%lx\n", rev_maj, rev_min >> 4,
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ei.bei_entry);
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#ifdef PCIBIOSVERBOSE
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printf("pcibios: config mechanism %s%s, special cycles %s%s, "
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"last bus %d\n",
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mech1 ? "[1]" : "[x]",
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mech2 ? "[2]" : "[x]",
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scmech1 ? "[1]" : "[x]",
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scmech2 ? "[2]" : "[x]",
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pcibios_max_bus);
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#endif
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/*
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* The PCI BIOS tells us the config mechanism; fill it in now
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* so that pci_mode_detect() doesn't have to look for it.
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*/
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pci_mode = mech1 ? 1 : 2;
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pcibios_present = 1;
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/*
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* Find the PCI IRQ Routing table.
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*/
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pcibios_pir_init();
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#ifdef PCIBIOS_INTR_FIXUP
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if (pcibios_pir_table != NULL) {
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int rv;
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u_int16_t pciirq;
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/*
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* Fixup interrupt routing.
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*/
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rv = pci_intr_fixup(NULL, I386_BUS_SPACE_IO, &pciirq);
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switch (rv) {
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case -1:
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/* Non-fatal error. */
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printf("Warning: unable to fix up PCI interrupt "
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"routing\n");
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break;
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case 1:
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/* Fatal error. */
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panic("pcibios_init: interrupt fixup failed");
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break;
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}
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/*
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* XXX Clear `pciirq' from the ISA interrupt allocation
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* XXX mask.
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*/
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}
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#endif
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#ifdef PCIBIOS_BUS_FIXUP
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pcibios_max_bus = pci_bus_fixup(NULL, 0);
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#ifdef PCIBIOSVERBOSE
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printf("PCI bus #%d is the last bus\n", pcibios_max_bus);
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#endif
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#endif
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}
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void
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pcibios_pir_init()
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{
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char devinfo[256];
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paddr_t pa;
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caddr_t p;
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unsigned char cksum;
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u_int16_t tablesize;
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u_int8_t rev_maj, rev_min;
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int i;
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for (pa = PCI_IRQ_TABLE_START; pa < PCI_IRQ_TABLE_END; pa += 16) {
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p = (caddr_t)ISA_HOLE_VADDR(pa);
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if (*(int *)p != BIOS32_MAKESIG('$', 'P', 'I', 'R'))
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continue;
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rev_min = *(p + 4);
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rev_maj = *(p + 5);
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tablesize = *(u_int16_t *)(p + 6);
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cksum = 0;
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for (i = 0; i < tablesize; i++)
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cksum += *(unsigned char *)(p + i);
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printf("PCI IRQ Routing Table rev. %d.%d found at 0x%lx, "
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"size %d bytes (%d entries)\n", rev_maj, rev_min, pa,
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tablesize, (tablesize - 32) / 16);
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if (cksum != 0) {
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printf("pcibios_pir_init: bad IRQ table checksum\n");
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continue;
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}
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if (tablesize < 32 || (tablesize % 16) != 0) {
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printf("pcibios_pir_init: bad IRQ table size\n");
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continue;
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}
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if (rev_maj != 1 || rev_min != 0) {
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printf("pcibios_pir_init: unsupported IRQ table "
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"version\n");
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continue;
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}
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/*
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* We can handle this table! Make a copy of it.
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*/
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memcpy(&pcibios_pir_header, p, 32);
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pcibios_pir_table = malloc(tablesize - 32, M_DEVBUF,
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M_NOWAIT);
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if (pcibios_pir_table == NULL) {
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printf("pcibios_pir_init: no memory for $PIR\n");
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return;
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}
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memcpy(pcibios_pir_table, p + 32, tablesize - 32);
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pcibios_pir_table_nentries = (tablesize - 32) / 16;
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printf("PCI Interrupt Router at %03d:%02d:%01d",
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pcibios_pir_header.router_bus,
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(pcibios_pir_header.router_devfunc >> 3) & 0x1f,
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pcibios_pir_header.router_devfunc & 7);
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if (pcibios_pir_header.compat_router != 0) {
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pci_devinfo(pcibios_pir_header.compat_router, 0, 0,
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devinfo);
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printf(" (%s)", devinfo);
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}
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printf("\n");
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pcibios_print_exclirq();
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#ifdef PCIINTR_DEBUG
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pcibios_print_pir_table();
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#endif
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return;
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}
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/*
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* If there was no PIR table found, try using the PCI BIOS
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* Get Interrupt Routing call.
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*
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* XXX The interface to this call sucks; just allocate enough
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* XXX room for 32 entries.
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*/
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pcibios_pir_table_nentries = 32;
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pcibios_pir_table = malloc(pcibios_pir_table_nentries *
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sizeof(*pcibios_pir_table), M_DEVBUF, M_NOWAIT);
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if (pcibios_pir_table == NULL) {
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printf("pcibios_pir_init: no memory for $PIR\n");
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return;
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}
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if (pcibios_get_intr_routing(pcibios_pir_table,
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&pcibios_pir_table_nentries,
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&pcibios_pir_header.exclusive_irq) != PCIBIOS_SUCCESS) {
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printf("No PCI IRQ Routing information available.\n");
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free(pcibios_pir_table, M_DEVBUF);
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pcibios_pir_table = NULL;
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pcibios_pir_table_nentries = 0;
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return;
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}
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printf("PCI BIOS has %d Interrupt Routing table entries\n",
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pcibios_pir_table_nentries);
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pcibios_print_exclirq();
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#ifdef PCIINTR_DEBUG
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pcibios_print_pir_table();
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#endif
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}
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int
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pcibios_get_status(rev_maj, rev_min, mech1, mech2, scmech1, scmech2, maxbus)
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u_int32_t *rev_maj, *rev_min, *mech1, *mech2, *scmech1, *scmech2,
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*maxbus;
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{
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u_int16_t ax, bx, cx;
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u_int32_t edx;
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int rv;
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__asm __volatile("lcall (%%edi) ; \
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jc 1f ; \
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xor %%ah, %%ah ; \
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1:"
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: "=a" (ax), "=b" (bx), "=c" (cx), "=d" (edx)
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: "0" (0xb101), "D" (&pcibios_entry));
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rv = pcibios_return_code(ax, "pcibios_get_status");
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if (rv != PCIBIOS_SUCCESS)
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return (rv);
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if (edx != BIOS32_MAKESIG('P', 'C', 'I', ' '))
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return (PCIBIOS_SERVICE_NOT_PRESENT); /* XXX */
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/*
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* Fill in the various pieces if info we're looking for.
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*/
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*mech1 = ax & 1;
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*mech2 = ax & (1 << 1);
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*scmech1 = ax & (1 << 4);
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*scmech2 = ax & (1 << 5);
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*rev_maj = (bx >> 8) & 0xff;
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*rev_min = bx & 0xff;
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*maxbus = cx & 0xff;
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return (PCIBIOS_SUCCESS);
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}
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int
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pcibios_get_intr_routing(table, nentries, exclirq)
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struct pcibios_intr_routing *table;
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int *nentries;
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u_int16_t *exclirq;
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{
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u_int16_t ax, bx;
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int rv;
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struct {
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u_int16_t size;
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caddr_t offset;
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u_int16_t segment;
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} __attribute__((__packed__)) args;
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args.size = *nentries * sizeof(*table);
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args.offset = (caddr_t)table;
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args.segment = GSEL(GDATA_SEL, SEL_KPL);
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memset(table, 0, args.size);
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__asm __volatile("lcall (%%esi) ; \
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jc 1f ; \
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xor %%ah, %%ah ; \
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1: movw %w2, %%ds ; \
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movw %w2, %%es"
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: "=a" (ax), "=b" (bx)
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: "r" GSEL(GDATA_SEL, SEL_KPL), "0" (0xb10e), "1" (0),
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"D" (&args), "S" (&pcibios_entry));
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rv = pcibios_return_code(ax, "pcibios_get_intr_routing");
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if (rv != PCIBIOS_SUCCESS)
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return (rv);
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*nentries = args.size / sizeof(*table);
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*exclirq = bx;
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return (PCIBIOS_SUCCESS);
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}
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int
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pcibios_return_code(ax, func)
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u_int16_t ax;
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const char *func;
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{
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const char *errstr;
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int rv = ax >> 8;
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switch (rv) {
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case PCIBIOS_SUCCESS:
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return (PCIBIOS_SUCCESS);
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case PCIBIOS_SERVICE_NOT_PRESENT:
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errstr = "service not present";
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break;
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case PCIBIOS_FUNCTION_NOT_SUPPORTED:
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errstr = "function not supported";
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break;
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case PCIBIOS_BAD_VENDOR_ID:
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errstr = "bad vendor ID";
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break;
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case PCIBIOS_DEVICE_NOT_FOUND:
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errstr = "device not found";
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break;
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case PCIBIOS_BAD_REGISTER_NUMBER:
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errstr = "bad register number";
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break;
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case PCIBIOS_SET_FAILED:
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errstr = "set failed";
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break;
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case PCIBIOS_BUFFER_TOO_SMALL:
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errstr = "buffer too small";
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break;
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default:
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printf("%s: unknown return code 0x%x\n", func, rv);
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return (rv);
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}
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printf("%s: %s\n", func, errstr);
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return (rv);
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}
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void
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pcibios_print_exclirq()
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{
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int i;
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if (pcibios_pir_header.exclusive_irq) {
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printf("PCI Exclusive IRQs:");
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for (i = 0; i < 16; i++) {
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if (pcibios_pir_header.exclusive_irq & (1 << i))
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printf(" %d", i);
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}
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printf("\n");
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}
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}
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#ifdef PCIINTR_DEBUG
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void
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pcibios_print_pir_table()
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{
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int i, j;
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for (i = 0; i < pcibios_pir_table_nentries; i++) {
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printf("PIR Entry %d:\n", i);
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printf("\tBus: %d Device: %d\n",
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pcibios_pir_table[i].bus,
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pcibios_pir_table[i].device >> 3);
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for (j = 0; j < 4; j++) {
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printf("\t\tINT%c: link 0x%02x bitmap 0x%04x\n",
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'A' + j,
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pcibios_pir_table[i].linkmap[j].link,
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pcibios_pir_table[i].linkmap[j].bitmap);
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}
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}
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}
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#endif
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