3eb244d801
sys/stdarg.h and expect compiler to provide proper builtins, defaulting to the GCC interface. lint still has a special fallback. Reduce abuse of _BSD_VA_LIST_ by defining __va_list by default and derive va_list as required by standards.
150 lines
5.8 KiB
C
150 lines
5.8 KiB
C
/*-
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $Id: ah_osdep.h,v 1.2 2011/07/17 20:54:51 joerg Exp $
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*/
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#ifndef _ATH_AH_OSDEP_H_
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#define _ATH_AH_OSDEP_H_
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/*
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* Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/bus.h>
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/*
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* Delay n microseconds.
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*/
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extern void ath_hal_delay(int);
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#define OS_DELAY(_n) ath_hal_delay(_n)
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#define OS_INLINE __inline
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#define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n))
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extern void ath_hal_memzero(void *, size_t);
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#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
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extern void *ath_hal_memcpy(void *, const void *, size_t);
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#define abs(_a) __builtin_abs(_a)
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struct ath_hal;
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extern u_int32_t ath_hal_getuptime(struct ath_hal *);
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#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
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/*
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* WiSoC boards overload the bus tag with information about the
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* board layout. We must extract the bus space tag from that
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* indirect structure. For everyone else the tag is passed in
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* directly.
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* XXX cache indirect ref privately
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*/
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#ifdef AH_SUPPORT_AR5312
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#define BUSTAG(ah) \
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((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)
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#define BUSHANDLE(ah) ((bus_space_handle_t)((ah)->ah_sh))
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#elif defined(AH_REGOPS_FUNC)
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#define BUSTAG(ah) (*(bus_space_tag_t *) (ah)->ah_st)
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#define BUSHANDLE(ah) (*(bus_space_handle_t *)((ah)->ah_sh))
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#define HALTAG(t) (HAL_BUS_TAG) &(t)
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#define HALHANDLE(h) (HAL_BUS_HANDLE) &(h)
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#else
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#define BUSTAG(ah) ((bus_space_tag_t) (ah)->ah_st)
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#define BUSHANDLE(ah) ((bus_space_handle_t) ((ah)->ah_sh))
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#define HALTAG(t) (HAL_BUS_TAG) (t)
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#define HALHANDLE(h) (HAL_BUS_HANDLE) (h)
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#endif
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/*
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* Register read/write; we assume the registers will always
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* be memory-mapped. Note that register accesses are done
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* using target-specific functions when debugging is enabled
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* (ATHHAL_DEBUG) or we are explicitly configured this way. The
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* latter is used on some platforms where the full i/o space
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* cannot be directly mapped.
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*/
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#if defined(ATHHAL_DEBUG) || defined(AH_REGOPS_FUNC) || defined(ATHHAL_DEBUG_ALQ)
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#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
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#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
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extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
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extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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#else
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/*
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* The hardware registers are native little-endian byte order.
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* Big-endian hosts are handled by enabling hardware byte-swap
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* of register reads and writes at reset. But the PCI clock
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* domain registers are not byte swapped! Thus, on big-endian
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* platforms we have to byte-swap thoese registers specifically.
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* Most of this code is collapsed at compile time because the
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* register values are constants.
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*/
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#define AH_LITTLE_ENDIAN 1234
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#define AH_BIG_ENDIAN 4321
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#if _BYTE_ORDER == _BIG_ENDIAN
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#define OS_REG_WRITE(_ah, _reg, _val) do { \
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if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
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bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
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(_reg), (_val)); \
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else \
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bus_space_write_stream_4((_ah)->ah_st, (_ah)->ah_sh, \
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(_reg), (_val)); \
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} while (0)
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#define OS_REG_READ(_ah, _reg) \
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(((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
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bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)) : \
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bus_space_read_stream_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#define OS_REG_WRITE(_ah, _reg, _val) \
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bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
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#define OS_REG_READ(_ah, _reg) \
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((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
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#endif /* _BYTE_ORDER */
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#endif /* ATHHAL_DEBUG || AH_REGFUNC || ATHHAL_DEBUG_ALQ */
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#ifdef ATHHAL_DEBUG_ALQ
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extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
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#else
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#define OS_MARK(_ah, _id, _v)
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#endif
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typedef void * HAL_SOFTC; /* pointer to driver/OS state */
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typedef bus_space_tag_t HAL_BUS_TAG; /* opaque bus i/o id tag */
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typedef bus_space_handle_t HAL_BUS_HANDLE; /* opaque bus i/o handle */
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#define OS_SET_DECLARE(set, ptype) __link_set_decl(set, ptype)
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#define OS_DATA_SET(set, sym) __link_set_add_rodata(set, sym)
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#define OS_SET_FOREACH(pvar, set) __link_set_foreach(pvar, set)
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#define __bswap16(x) bswap16(x)
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#define __bswap32(x) bswap32(x)
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#endif /* _ATH_AH_OSDEP_H_ */
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