160 lines
5.1 KiB
ArmAsm
160 lines
5.1 KiB
ArmAsm
/* $NetBSD: armadaxp_start.S,v 1.3 2014/03/29 14:53:57 matt Exp $ */
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/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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Developed by Semihalf
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********************************************************************************
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Marvell BSD License
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#include "opt_cputypes.h"
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#include <evbarm/marvell/marvellreg.h>
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#include <evbarm/marvell/marvellvar.h>
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#include "assym.h"
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RCSID("$NetBSD: armadaxp_start.S,v 1.3 2014/03/29 14:53:57 matt Exp $")
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#ifdef KERNEL_BASES_EQUAL
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#error KERNEL_BASE_VIRT should not equal KERNEL_BASE_PHYS
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#endif
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/*
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* We don't want to hard-code some basic things like RAM start etc.
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* Hence, it is important to set the following options to resanoable values
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* in std.armadaxp configuration file.
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*/
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#if !defined(STARTUP_PAGETABLE_ADDR)
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#error STARTUP_PAGETABLE_ADDR not defined. Please define it in std.armadaxp
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#elif !defined(MEMSTART)
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#error MEMSTART not defined. Please define it in std.armadaxp
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#endif
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.section .start,"ax",%progbits
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.global _C_LABEL(armadaxp_start)
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_C_LABEL(armadaxp_start):
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/* Move into supervisor mode and disable IRQs/FIQs. */
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cpsid if, #PSR_SVC32_MODE
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/* Disable MMU for a while */
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mrc p15, 0, r2, c1, c0, 0
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movw r1, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
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CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_IC_ENABLE |\
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CPU_CONTROL_BPRD_ENABLE)
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bic r2, r2, r1
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mcr p15, 0, r2, c1, c0, 0
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dsb
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isb
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/* build page table from scratch */
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movw r0, #:lower16:STARTUP_PAGETABLE_ADDR
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movt r0, #:upper16:STARTUP_PAGETABLE_ADDR
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adr r4, mmu_init_table
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b 3f
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2: str r3, [r0, r2]
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add r2, r2, #4
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add r3, r3, #(L1_S_SIZE)
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adds r1, r1, #-1
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bhi 2b
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3:
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ldmia r4!, {r1,r2,r3} /* # of sections, VA, PA|attr */
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cmp r1, #0
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bne 2b
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mcr p15, 0, r0, c2, c0, 0 // Set TTBR0
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#ifdef ARM_MMU_EXTENDED
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mcr p15, 0, r0, c2, c0, 1 // Set TTBR1
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mov r0, #TTBCR_S_N_1
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#else
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mov r0, #0
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#endif
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mcr p15, 0, r0, c2, c0, 2 // TTBCR write
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
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mcr p15, 0, r0, c13, c0, 1 // CONTEXTIDR write: Set ASID to 0
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/* Set the Domain Access register. Very important! */
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mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r0, c3, c0, 0 // DACR write
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#define CPU_CONTROL_SET (CPU_CONTROL_XP_ENABLE | CPU_CONTROL_IC_ENABLE \
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| CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
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/* Enable MMU */
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mrc p15, 0, r0, c1, c0, 0
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movw r1, #:lower16:CPU_CONTROL_SET
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#if (CPU_CONTROL_SET & 0xffff) != 0
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movt r1, #:upper16:CPU_CONTROL_SET
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#endif
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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isb
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dsb
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/* Jump to kernel code in TRUE VA */
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movw ip, #:lower16:start
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movt ip, #:upper16:start
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bx ip
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/* NOTREACHED */
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#define MMU_INIT(va,pa,n_sec,attr) \
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.word n_sec ; \
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.word 4*((va)>>L1_S_SHIFT) ; \
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.word (pa)|(attr) ;
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mmu_init_table:
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/* fill all table VA==PA */
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/* map SDRAM VA==PA, WT cacheable */
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MMU_INIT(MEMSTART, MEMSTART, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW)
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/* map VA 0x80000000..0x83ffffff to PA */
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MMU_INIT(KERNEL_BASE_EXT, MEMSTART, 64, L1_TYPE_S|L1_S_C|L1_S_AP_KRW)
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/*
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* In case of early start debugging it might be useful to map
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* SoC registers (for UART access).
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*/
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MMU_INIT(MARVELL_INTERREGS_PBASE, MARVELL_INTERREGS_PBASE, 1,
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L1_TYPE_S|L1_S_PROTO|L1_S_AP_KRW)
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MMU_INIT(MARVELL_INTERREGS_VBASE, MARVELL_INTERREGS_PBASE, 1,
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L1_TYPE_S|L1_S_PROTO|L1_S_AP_KRW)
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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