191 lines
8.5 KiB
C
191 lines
8.5 KiB
C
/* $NetBSD: mtpr.h,v 1.20 2007/02/16 01:34:03 matt Exp $ */
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/*
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* Copyright (c) 1994 Ludd, University of Lule}, Sweden.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed at Ludd, University of Lule}.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* All bugs are subject to removal without further notice */
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#ifndef _VAX_MTPR_H_
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#define _VAX_MTPR_H_
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/******************************************************************************
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Processor register numbers in the VAX /IC
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******************************************************************************/
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#define PR_KSP 0 /* Kernel Stack Pointer */
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#define PR_ESP 1 /* Executive Stack Pointer */
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#define PR_SSP 2 /* Supervisor Stack Pointer */
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#define PR_USP 3 /* User Stack Pointer */
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#define PR_ISP 4 /* Interrupt Stack Pointer */
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#define PR_P0BR 8 /* P0 Base Register */
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#define PR_P0LR 9 /* P0 Length Register */
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#define PR_P1BR 10 /* P1 Base Register */
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#define PR_P1LR 11 /* P1 Length Register */
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#define PR_SBR 12 /* System Base Register */
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#define PR_SLR 13 /* System Limit Register */
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#define PR_PCBB 16 /* Process Control Block Base */
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#define PR_SCBB 17 /* System Control Block Base */
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#define PR_IPL 18 /* Interrupt Priority Level */
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#define PR_ASTLVL 19 /* AST Level */
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#define PR_SIRR 20 /* Software Interrupt Request */
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#define PR_SISR 21 /* Software Interrupt Summary */
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#define PR_IPIR 22 /* KA820 Interprocessor register */
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#define PR_MCSR 23 /* Machine Check Status Register 11/750 */
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#define PR_ICCS 24 /* Interval Clock Control */
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#define PR_NICR 25 /* Next Interval Count */
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#define PR_ICR 26 /* Interval Count */
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#define PR_TODR 27 /* Time Of Year (optional) */
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#define PR_CSRS 28 /* Console Storage R/S */
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#define PR_CSRD 29 /* Console Storage R/D */
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#define PR_CSTS 30 /* Console Storage T/S */
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#define PR_CSTD 31 /* Console Storage T/D */
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#define PR_RXCS 32 /* Console Receiver C/S */
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#define PR_RXDB 33 /* Console Receiver D/B */
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#define PR_TXCS 34 /* Console Transmit C/S */
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#define PR_TXDB 35 /* Console Transmit D/B */
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#define PR_TBDR 36 /* Translation Buffer Group Disable Register 11/750 */
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#define PR_CADR 37 /* Cache Disable Register 11/750 */
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#define PR_MCESR 38 /* Machiune Check Error Summary Register 11/750 */
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#define PR_CAER 39 /* Cache Error Register 11/750 */
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#define PR_ACCS 40 /* Accelerator control register */
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#define PR_SAVISP 41 /* Console Saved ISP */
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#define PR_SAVPC 42 /* Console Saved PC */
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#define PR_SAVPSL 43 /* Console Saved PSL */
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#define PR_WCSA 44 /* WCS Address */
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#define PR_WCSB 45 /* WCS Data */
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#define PR_SBIFS 48 /* SBI Fault/Status */
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#define PR_SBIS 49 /* SBI Silo */
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#define PR_SBISC 50 /* SBI Silo Comparator */
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#define PR_SBIMT 51 /* SBI Silo Maintenance */
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#define PR_SBIER 52 /* SBI Error Register */
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#define PR_SBITA 53 /* SBI Timeout Address Register */
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#define PR_SBIQC 54 /* SBI Quadword Clear */
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#define PR_IUR 55 /* Initialize Unibus Register 11/750 */
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#define PR_MAPEN 56 /* Memory Management Enable */
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#define PR_TBIA 57 /* Trans. Buf. Invalidate All */
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#define PR_TBIS 58 /* Trans. Buf. Invalidate Single */
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#define PR_TBDATA 59 /* Translation Buffer Data */
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#define PR_MBRK 60 /* Microprogram Break */
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#define PR_PMR 61 /* Performance Monnitor Enable */
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#define PR_SID 62 /* System ID Register */
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#define PR_TBCHK 63 /* Translation Buffer Check */
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#define PR_PAMACC 64 /* Physical Address Memory Map Access (KA86) */
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#define PR_PAMLOC 65 /* Physical Address Memory Map Location (KA86) */
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#define PR_CSWP 66 /* Cache Sweep (KA86) */
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#define PR_MDECC 67 /* MBOX Data Ecc Register (KA86) */
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#define PR_MENA 68 /* MBOX Error Enable Register (KA86) */
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#define PR_MDCTL 69 /* MBOX Data Control Register (KA86) */
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#define PR_MCCTL 70 /* MBOX Mcc Control Register (KA86) */
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#define PR_MERG 71 /* MBOX Error Generator Register (KA86) */
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#define PR_CRBT 72 /* Console Reboot (KA86) */
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#define PR_DFI 73 /* Diagnostic Fault Insertion Register (KA86) */
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#define PR_EHSR 74 /* Error Handling Status Register (KA86) */
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#define PR_STXCS 76 /* Console Storage C/S (KA86) */
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#define PR_STXDB 77 /* Console Storage D/B (KA86) */
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#define PR_ESPA 78 /* EBOX Scratchpad Address (KA86) */
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#define PR_ESPD 79 /* EBOX Scratchpad Data (KA86) */
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#define PR_RXCS1 80 /* Serial-Line Unit 1 Receive CSR (KA820) */
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#define PR_RXDB1 81 /* Serial-Line Unit 1 Receive Data Buffer (KA820) */
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#define PR_TXCS1 82 /* Serial-Line Unit 1 Transmit CSR (KA820) */
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#define PR_TXDB1 83 /* Serial-Line Unit 1 Transmit Data Buffer (KA820) */
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#define PR_RXCS2 84 /* Serial-Line Unit 2 Receive CSR (KA820) */
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#define PR_RXDB2 85 /* Serial-Line Unit 2 Receive Data Buffer (KA820) */
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#define PR_TXCS2 86 /* Serial-Line Unit 2 Transmit CSR (KA820) */
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#define PR_TXDB2 87 /* Serial-Line Unit 2 Transmit Data Buffer (KA820) */
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#define PR_RXCS3 88 /* Serial-Line Unit 3 Receive CSR (KA820) */
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#define PR_RXDB3 89 /* Serial-Line Unit 3 Receive Data Buffer (KA820) */
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#define PR_TXCS3 90 /* Serial-Line Unit 3 Transmit CSR (KA820) */
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#define PR_TXDB3 91 /* Serial-Line Unit 3 Transmit Data Buffer (KA820) */
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#define PR_RXCD 92 /* Receive Console Data from another CPU (KA820) */
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#define PR_CACHEX 93 /* Cache invalidate Register (KA820) */
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#define PR_BINID 94 /* VAXBI node ID Register (KA820) */
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#define PR_BISTOP 95 /* VAXBI Stop Register (KA820) */
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#define PR_BCBTS 113 /* Backup Cache Tag Store (KA670) */
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#define PR_BCP1TS 114 /* Primary Tag Store 1st half (KA670) */
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#define PR_BCP2TS 115 /* Primary Tag Store 2st half (KA670) */
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#define PR_BCRFR 116 /* Refresh Register (KA670) */
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#define PR_BCIDX 117 /* Index Register (KA670) */
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#define PR_BCSTS 118 /* Status (KA670) */
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#define PR_BCCTL 119 /* Control Register (KA670) */
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#define PR_BCERR 120 /* Error Address (KA670) */
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#define PR_BCFBTS 121 /* Flush backup tag store (KA670) */
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#define PR_BCFPTS 122 /* Flush primary tag store (KA670) */
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#define PR_VINTSR 123 /* vector i/f error status (KA43/KA46) */
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#define PR_PCTAG 124 /* primary cache tag store (KA43/KA46) */
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#define PR_PCIDX 125 /* primary cache index (KA43/KA46) */
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#define PR_PCERR 126 /* primary cache error address (KA43/KA46) */
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#define PR_PCSTS 127 /* primary cache status (KA43/KA46) */
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#define PR_VPSR 144 /* Vector processor status register */
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#define PR_VAER 145 /* Vector arithmetic error register */
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#define PR_VMAC 146 /* Vector memory activity register */
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#define PR_VTBIA 147 /* Vector TBIA */
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#define PR_VSAR 148 /* Vector state address register */
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#define PR_VIADR 157 /* Vector indirect address register */
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#define PR_VIDLO 158 /* Vector indirect data low */
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#define PR_VIDHI 159 /* Vector indirect data high */
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/* Definitions for AST */
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#define AST_NO 4
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#define AST_OK 3
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#ifndef _LOCORE
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static inline void
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mtpr(register_t val, int reg)
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{
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__asm volatile (
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"mtpr %0,%1"
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: /* No output */
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: "g" (val), "g" (reg));
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}
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static inline register_t
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mfpr(int reg)
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{
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register_t __val;
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__asm volatile (
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"mfpr %1,%0"
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: "=g" (__val)
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: "g" (reg));
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return __val;
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}
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#endif /* _LOCORE */
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#endif /* _VAX_MTPR_H_ */
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