76 lines
3.3 KiB
C
76 lines
3.3 KiB
C
/* $NetBSD: z8530var.h,v 1.6 1996/12/17 21:00:54 gwr Exp $ */
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/*
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* Copyright (c) 1994 Gordon W. Ross
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)zsvar.h 8.1 (Berkeley) 6/11/93
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*/
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#include <dev/ic/z8530sc.h>
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struct zsc_softc {
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struct device zsc_dev; /* required first: base device */
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struct zs_chanstate *zsc_cs[2]; /* channel A and B soft state */
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/* Machine-dependent part follows... */
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struct zs_chanstate zsc_cs_store[2];
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};
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/*
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* Functions to read and write individual registers in a channel.
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* The ZS chip requires a 1.6 uSec. recovery time between accesses,
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* and the Sun3 hardware does NOT take care of this for you.
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* The delay is now handled inside the chip access functions.
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* These could be inlines, but with the delay, speed is moot.
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*/
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u_char zs_read_reg __P((struct zs_chanstate *cs, u_char reg));
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u_char zs_read_csr __P((struct zs_chanstate *cs));
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u_char zs_read_data __P((struct zs_chanstate *cs));
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void zs_write_reg __P((struct zs_chanstate *cs, u_char reg, u_char val));
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void zs_write_csr __P((struct zs_chanstate *cs, u_char val));
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void zs_write_data __P((struct zs_chanstate *cs, u_char val));
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/* Zilog Serial hardware interrupts (hard-wired at 6) */
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#define splzs() spl6()
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