699 lines
18 KiB
C
699 lines
18 KiB
C
/* $NetBSD: fpu_calcea.c,v 1.24 2011/05/25 15:47:19 tsutsui Exp $ */
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/*
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* Copyright (c) 1995 Gordon W. Ross
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* portion Copyright (c) 1995 Ken Nakata
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* 4. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Gordon Ross
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_m68k_arch.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: fpu_calcea.c,v 1.24 2011/05/25 15:47:19 tsutsui Exp $");
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#include <sys/param.h>
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#include <sys/signal.h>
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#include <sys/systm.h>
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#include <machine/frame.h>
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#include <m68k/m68k.h>
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#include "fpu_emulate.h"
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#ifdef DEBUG_FPE
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#define DPRINTF(x) printf x
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#else
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#define DPRINTF(x) do {} while (/* CONSTCOND */ 0)
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#endif
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/*
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* Prototypes of static functions
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*/
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static int decode_ea6(struct frame *, struct instruction *,
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struct insn_ea *, int);
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static int fetch_immed(struct frame *, struct instruction *, int *);
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static int fetch_disp(struct frame *, struct instruction *, int, int *);
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static int calc_ea(struct insn_ea *, char *, char **);
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/*
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* Helper routines for dealing with "effective address" values.
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*/
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/*
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* Decode an effective address into internal form.
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* Returns zero on success, else signal number.
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*/
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int
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fpu_decode_ea(struct frame *frame, struct instruction *insn,
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struct insn_ea *ea, int modreg)
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{
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int sig;
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#ifdef DIAGNOSTIC
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if (insn->is_datasize < 0)
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panic("%s: called with uninitialized datasize", __func__);
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#endif
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sig = 0;
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/* Set the most common value here. */
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ea->ea_regnum = 8 + (modreg & 7);
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if ((modreg & 060) == 0) {
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/* register direct */
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ea->ea_regnum = modreg & 0xf;
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ea->ea_flags = EA_DIRECT;
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DPRINTF(("%s: register direct reg=%d\n",
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__func__, ea->ea_regnum));
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} else if ((modreg & 077) == 074) {
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/* immediate */
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ea->ea_flags = EA_IMMED;
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sig = fetch_immed(frame, insn, &ea->ea_immed[0]);
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DPRINTF(("%s: immediate size=%d\n",
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__func__, insn->is_datasize));
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}
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/*
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* rest of the address modes need to be separately
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* handled for the LC040 and the others.
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*/
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#if 0 /* XXX */
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else if (frame->f_format == 4 && frame->f_fmt4.f_fa) {
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/* LC040 */
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ea->ea_flags = EA_FRAME_EA;
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ea->ea_fea = frame->f_fmt4.f_fa;
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DPRINTF(("%s: 68LC040 - in-frame EA (%p) size %d\n",
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__func__, (void *)ea->ea_fea, insn->is_datasize));
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if ((modreg & 070) == 030) {
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/* postincrement mode */
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ea->ea_flags |= EA_POSTINCR;
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} else if ((modreg & 070) == 040) {
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/* predecrement mode */
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ea->ea_flags |= EA_PREDECR;
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#ifdef M68060
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#if defined(M68020) || defined(M68030) || defined(M68040)
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if (cputype == CPU_68060)
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#endif
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if (insn->is_datasize == 12)
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ea->ea_fea -= 8;
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#endif
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}
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}
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#endif /* XXX */
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else {
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/* 020/030 */
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switch (modreg & 070) {
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case 020: /* (An) */
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ea->ea_flags = 0;
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DPRINTF(("%s: register indirect reg=%d\n",
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__func__, ea->ea_regnum));
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break;
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case 030: /* (An)+ */
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ea->ea_flags = EA_POSTINCR;
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DPRINTF(("%s: reg indirect postincrement reg=%d\n",
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__func__, ea->ea_regnum));
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break;
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case 040: /* -(An) */
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ea->ea_flags = EA_PREDECR;
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DPRINTF(("%s: reg indirect predecrement reg=%d\n",
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__func__, ea->ea_regnum));
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break;
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case 050: /* (d16,An) */
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ea->ea_flags = EA_OFFSET;
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sig = fetch_disp(frame, insn, 1, &ea->ea_offset);
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DPRINTF(("%s: reg indirect with displacement reg=%d\n",
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__func__, ea->ea_regnum));
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break;
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case 060: /* (d8,An,Xn) */
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ea->ea_flags = EA_INDEXED;
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sig = decode_ea6(frame, insn, ea, modreg);
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break;
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case 070: /* misc. */
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ea->ea_regnum = (modreg & 7);
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switch (modreg & 7) {
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case 0: /* (xxxx).W */
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ea->ea_flags = EA_ABS;
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sig = fetch_disp(frame, insn, 1,
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&ea->ea_absaddr);
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DPRINTF(("%s: absolute address (word)\n",
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__func__));
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break;
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case 1: /* (xxxxxxxx).L */
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ea->ea_flags = EA_ABS;
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sig = fetch_disp(frame, insn, 2,
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&ea->ea_absaddr);
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DPRINTF(("%s: absolute address (long)\n",
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__func__));
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break;
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case 2: /* (d16,PC) */
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ea->ea_flags = EA_PC_REL | EA_OFFSET;
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sig = fetch_disp(frame, insn, 1,
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&ea->ea_absaddr);
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DPRINTF(("%s: pc relative word displacement\n",
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__func__));
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break;
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case 3: /* (d8,PC,Xn) */
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ea->ea_flags = EA_PC_REL | EA_INDEXED;
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sig = decode_ea6(frame, insn, ea, modreg);
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break;
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case 4: /* #data */
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/* it should have been taken care of earlier */
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default:
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DPRINTF(("%s: invalid addr mode (7,%d)\n",
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__func__, modreg & 7));
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return SIGILL;
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}
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break;
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}
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}
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ea->ea_moffs = 0;
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return sig;
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}
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/*
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* Decode Mode=6 address modes
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*/
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static int
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decode_ea6(struct frame *frame, struct instruction *insn, struct insn_ea *ea,
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int modreg)
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{
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int extword, idx;
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int basedisp, outerdisp;
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int bd_size, od_size;
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int sig;
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extword = fusword((void *)(insn->is_pc + insn->is_advance));
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if (extword < 0) {
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return SIGSEGV;
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}
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insn->is_advance += 2;
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/* get register index */
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ea->ea_idxreg = (extword >> 12) & 0xf;
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idx = frame->f_regs[ea->ea_idxreg];
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if ((extword & 0x0800) == 0) {
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/* if word sized index, sign-extend */
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idx &= 0xffff;
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if (idx & 0x8000) {
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idx |= 0xffff0000;
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}
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}
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/* scale register index */
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idx <<= ((extword >> 9) & 3);
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if ((extword & 0x100) == 0) {
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/* brief extension word - sign-extend the displacement */
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basedisp = (extword & 0xff);
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if (basedisp & 0x80) {
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basedisp |= 0xffffff00;
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}
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ea->ea_basedisp = idx + basedisp;
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ea->ea_outerdisp = 0;
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DPRINTF(("%s: brief ext word idxreg=%d, basedisp=%08x\n",
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__func__, ea->ea_idxreg, ea->ea_basedisp));
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} else {
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/* full extension word */
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if (extword & 0x80) {
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ea->ea_flags |= EA_BASE_SUPPRSS;
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}
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bd_size = ((extword >> 4) & 3) - 1;
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od_size = (extword & 3) - 1;
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sig = fetch_disp(frame, insn, bd_size, &basedisp);
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if (sig)
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return sig;
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if (od_size >= 0)
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ea->ea_flags |= EA_MEM_INDIR;
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sig = fetch_disp(frame, insn, od_size, &outerdisp);
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if (sig)
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return sig;
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switch (extword & 0x44) {
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case 0: /* preindexed */
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ea->ea_basedisp = basedisp + idx;
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ea->ea_outerdisp = outerdisp;
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break;
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case 4: /* postindexed */
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ea->ea_basedisp = basedisp;
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ea->ea_outerdisp = outerdisp + idx;
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break;
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case 0x40: /* no index */
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ea->ea_basedisp = basedisp;
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ea->ea_outerdisp = outerdisp;
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break;
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default:
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DPRINTF(("%s: invalid indirect mode: ext word %04x\n",
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__func__, extword));
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return SIGILL;
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break;
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}
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DPRINTF(("%s: full ext idxreg=%d, basedisp=%x, outerdisp=%x\n",
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__func__,
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ea->ea_idxreg, ea->ea_basedisp, ea->ea_outerdisp));
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}
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DPRINTF(("%s: regnum=%d, flags=%x\n",
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__func__, ea->ea_regnum, ea->ea_flags));
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return 0;
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}
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/*
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* Load a value from an effective address.
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* Returns zero on success, else signal number.
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*/
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int
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fpu_load_ea(struct frame *frame, struct instruction *insn, struct insn_ea *ea,
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char *dst)
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{
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int *reg;
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char *src;
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int len, step;
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int sig;
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#ifdef DIAGNOSTIC
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if (ea->ea_regnum & ~0xF)
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panic("%s: bad regnum", __func__);
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#endif
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DPRINTF(("%s: frame at %p\n", __func__, frame));
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/* dst is always int or larger. */
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len = insn->is_datasize;
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if (len < 4)
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dst += (4 - len);
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step = (len == 1 && ea->ea_regnum == 15 /* sp */) ? 2 : len;
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#if 0
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if (ea->ea_flags & EA_FRAME_EA) {
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/* Using LC040 frame EA */
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#ifdef DEBUG_FPE
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if (ea->ea_flags & (EA_PREDECR|EA_POSTINCR)) {
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printf("%s: frame ea %08x w/r%d\n",
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__func__, ea->ea_fea, ea->ea_regnum);
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} else {
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printf("%s: frame ea %08x\n", __func__, ea->ea_fea);
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}
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#endif
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src = (char *)ea->ea_fea;
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copyin(src + ea->ea_moffs, dst, len);
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if (ea->ea_flags & EA_PREDECR) {
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frame->f_regs[ea->ea_regnum] = ea->ea_fea;
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ea->ea_fea -= step;
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ea->ea_moffs = 0;
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} else if (ea->ea_flags & EA_POSTINCR) {
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ea->ea_fea += step;
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frame->f_regs[ea->ea_regnum] = ea->ea_fea;
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ea->ea_moffs = 0;
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} else {
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ea->ea_moffs += step;
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}
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/* That's it, folks */
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} else
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#endif
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if (ea->ea_flags & EA_DIRECT) {
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if (len > 4) {
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DPRINTF(("%s: operand doesn't fit CPU reg\n",
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__func__));
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return SIGILL;
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}
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if (ea->ea_moffs > 0) {
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DPRINTF(("%s: more than one move from CPU reg\n",
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__func__));
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return SIGILL;
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}
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src = (char *)&frame->f_regs[ea->ea_regnum];
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/* The source is an int. */
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if (len < 4) {
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src += (4 - len);
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DPRINTF(("%s: short/byte opr - addr adjusted\n",
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__func__));
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}
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DPRINTF(("%s: src %p\n", __func__, src));
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memcpy(dst, src, len);
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} else if (ea->ea_flags & EA_IMMED) {
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DPRINTF(("%s: immed %08x%08x%08x size %d\n", __func__,
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ea->ea_immed[0], ea->ea_immed[1], ea->ea_immed[2], len));
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src = (char *)&ea->ea_immed[0];
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if (len < 4) {
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src += (4 - len);
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DPRINTF(("%s: short/byte immed opr - "
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"addr adjusted\n", __func__));
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}
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memcpy(dst, src, len);
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} else if (ea->ea_flags & EA_ABS) {
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DPRINTF(("%s: abs addr %08x\n", __func__, ea->ea_absaddr));
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src = (char *)ea->ea_absaddr;
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copyin(src, dst, len);
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} else /* register indirect */ {
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if (ea->ea_flags & EA_PC_REL) {
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DPRINTF(("%s: using PC\n", __func__));
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reg = NULL;
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/*
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* Grab the register contents. 4 is offset to the first
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* extension word from the opcode
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*/
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src = (char *)insn->is_pc + 4;
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DPRINTF(("%s: pc relative pc+4 = %p\n", __func__, src));
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} else /* not PC relative */ {
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DPRINTF(("%s: using register %c%d\n",
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__func__,
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(ea->ea_regnum >= 8) ? 'a' : 'd',
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ea->ea_regnum & 7));
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/* point to the register */
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reg = &frame->f_regs[ea->ea_regnum];
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if (ea->ea_flags & EA_PREDECR) {
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DPRINTF(("%s: predecr mode - "
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"reg decremented\n", __func__));
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*reg -= step;
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ea->ea_moffs = 0;
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}
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/* Grab the register contents. */
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src = (char *)*reg;
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DPRINTF(("%s: reg indirect reg = %p\n", __func__, src));
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}
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sig = calc_ea(ea, src, &src);
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if (sig)
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return sig;
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copyin(src + ea->ea_moffs, dst, len);
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/* do post-increment */
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if (ea->ea_flags & EA_POSTINCR) {
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if (ea->ea_flags & EA_PC_REL) {
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DPRINTF(("%s: tried to postincrement PC\n",
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__func__));
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return SIGILL;
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}
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*reg += step;
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ea->ea_moffs = 0;
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DPRINTF(("%s: postinc mode - reg incremented\n",
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__func__));
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} else {
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ea->ea_moffs += len;
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}
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}
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return 0;
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}
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/*
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* Store a value at the effective address.
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* Returns zero on success, else signal number.
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*/
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int
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fpu_store_ea(struct frame *frame, struct instruction *insn, struct insn_ea *ea,
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char *src)
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{
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int *reg;
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char *dst;
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int len, step;
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int sig;
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#ifdef DIAGNOSTIC
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if (ea->ea_regnum & ~0xf)
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panic("%s: bad regnum", __func__);
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#endif
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if (ea->ea_flags & (EA_IMMED|EA_PC_REL)) {
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/* not alterable address mode */
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DPRINTF(("%s: not alterable address mode\n", __func__));
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return SIGILL;
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}
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/* src is always int or larger. */
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len = insn->is_datasize;
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if (len < 4)
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src += (4 - len);
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step = (len == 1 && ea->ea_regnum == 15 /* sp */) ? 2 : len;
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if (ea->ea_flags & EA_FRAME_EA) {
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/* Using LC040 frame EA */
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#ifdef DEBUG_FPE
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if (ea->ea_flags & (EA_PREDECR|EA_POSTINCR)) {
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printf("%s: frame ea %08x w/r%d\n",
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__func__, ea->ea_fea, ea->ea_regnum);
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} else {
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printf("%s: frame ea %08x\n", __func__, ea->ea_fea);
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}
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#endif
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dst = (char *)ea->ea_fea;
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copyout(src, dst + ea->ea_moffs, len);
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if (ea->ea_flags & EA_PREDECR) {
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frame->f_regs[ea->ea_regnum] = ea->ea_fea;
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ea->ea_fea -= step;
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ea->ea_moffs = 0;
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} else if (ea->ea_flags & EA_POSTINCR) {
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ea->ea_fea += step;
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frame->f_regs[ea->ea_regnum] = ea->ea_fea;
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ea->ea_moffs = 0;
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} else {
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ea->ea_moffs += step;
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}
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/* That's it, folks */
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} else if (ea->ea_flags & EA_ABS) {
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DPRINTF(("%s: abs addr %08x\n", __func__, ea->ea_absaddr));
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dst = (char *)ea->ea_absaddr;
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copyout(src, dst + ea->ea_moffs, len);
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ea->ea_moffs += len;
|
|
} else if (ea->ea_flags & EA_DIRECT) {
|
|
if (len > 4) {
|
|
DPRINTF(("%s: operand doesn't fit CPU reg\n",
|
|
__func__));
|
|
return SIGILL;
|
|
}
|
|
if (ea->ea_moffs > 0) {
|
|
DPRINTF(("%s: more than one move to CPU reg\n",
|
|
__func__));
|
|
return SIGILL;
|
|
}
|
|
dst = (char *)&frame->f_regs[ea->ea_regnum];
|
|
/* The destination is an int. */
|
|
if (len < 4) {
|
|
dst += (4 - len);
|
|
DPRINTF(("%s: short/byte opr - dst addr adjusted\n",
|
|
__func__));
|
|
}
|
|
DPRINTF(("%s: dst %p\n", __func__, dst));
|
|
memcpy(dst, src, len);
|
|
} else /* One of MANY indirect forms... */ {
|
|
DPRINTF(("%s: using register %c%d\n", __func__,
|
|
(ea->ea_regnum >= 8) ? 'a' : 'd', ea->ea_regnum & 7));
|
|
/* point to the register */
|
|
reg = &(frame->f_regs[ea->ea_regnum]);
|
|
|
|
/* do pre-decrement */
|
|
if (ea->ea_flags & EA_PREDECR) {
|
|
DPRINTF(("%s: predecr mode - reg decremented\n",
|
|
__func__));
|
|
*reg -= step;
|
|
ea->ea_moffs = 0;
|
|
}
|
|
|
|
/* calculate the effective address */
|
|
sig = calc_ea(ea, (char *)*reg, &dst);
|
|
if (sig)
|
|
return sig;
|
|
|
|
DPRINTF(("%s: dst addr=%p+%d\n", __func__, dst, ea->ea_moffs));
|
|
copyout(src, dst + ea->ea_moffs, len);
|
|
|
|
/* do post-increment */
|
|
if (ea->ea_flags & EA_POSTINCR) {
|
|
*reg += step;
|
|
ea->ea_moffs = 0;
|
|
DPRINTF(("%s: postinc mode - reg incremented\n",
|
|
__func__));
|
|
} else {
|
|
ea->ea_moffs += len;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* fetch_immed: fetch immediate operand
|
|
*/
|
|
static int
|
|
fetch_immed(struct frame *frame, struct instruction *insn, int *dst)
|
|
{
|
|
int data, ext_bytes;
|
|
|
|
ext_bytes = insn->is_datasize;
|
|
|
|
if (0 < ext_bytes) {
|
|
data = fusword((void *)(insn->is_pc + insn->is_advance));
|
|
if (data < 0)
|
|
return SIGSEGV;
|
|
if (ext_bytes == 1) {
|
|
/* sign-extend byte to long */
|
|
data &= 0xff;
|
|
if (data & 0x80)
|
|
data |= 0xffffff00;
|
|
} else if (ext_bytes == 2) {
|
|
/* sign-extend word to long */
|
|
data &= 0xffff;
|
|
if (data & 0x8000)
|
|
data |= 0xffff0000;
|
|
}
|
|
insn->is_advance += 2;
|
|
dst[0] = data;
|
|
}
|
|
if (2 < ext_bytes) {
|
|
data = fusword((void *)(insn->is_pc + insn->is_advance));
|
|
if (data < 0)
|
|
return SIGSEGV;
|
|
insn->is_advance += 2;
|
|
dst[0] <<= 16;
|
|
dst[0] |= data;
|
|
}
|
|
if (4 < ext_bytes) {
|
|
data = fusword((void *)(insn->is_pc + insn->is_advance));
|
|
if (data < 0)
|
|
return SIGSEGV;
|
|
dst[1] = data << 16;
|
|
data = fusword((void *)(insn->is_pc + insn->is_advance + 2));
|
|
if (data < 0)
|
|
return SIGSEGV;
|
|
insn->is_advance += 4;
|
|
dst[1] |= data;
|
|
}
|
|
if (8 < ext_bytes) {
|
|
data = fusword((void *)(insn->is_pc + insn->is_advance));
|
|
if (data < 0)
|
|
return SIGSEGV;
|
|
dst[2] = data << 16;
|
|
data = fusword((void *)(insn->is_pc + insn->is_advance + 2));
|
|
if (data < 0)
|
|
return SIGSEGV;
|
|
insn->is_advance += 4;
|
|
dst[2] |= data;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* fetch_disp: fetch displacement in full extension words
|
|
*/
|
|
static int
|
|
fetch_disp(struct frame *frame, struct instruction *insn, int size, int *res)
|
|
{
|
|
int disp, word;
|
|
|
|
if (size == 1) {
|
|
word = fusword((void *)(insn->is_pc + insn->is_advance));
|
|
if (word < 0)
|
|
return SIGSEGV;
|
|
disp = word & 0xffff;
|
|
if (disp & 0x8000) {
|
|
/* sign-extend */
|
|
disp |= 0xffff0000;
|
|
}
|
|
insn->is_advance += 2;
|
|
} else if (size == 2) {
|
|
word = fusword((void *)(insn->is_pc + insn->is_advance));
|
|
if (word < 0)
|
|
return SIGSEGV;
|
|
disp = word << 16;
|
|
word = fusword((void *)(insn->is_pc + insn->is_advance + 2));
|
|
if (word < 0)
|
|
return SIGSEGV;
|
|
disp |= (word & 0xffff);
|
|
insn->is_advance += 4;
|
|
} else {
|
|
disp = 0;
|
|
}
|
|
*res = disp;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Calculates an effective address for all address modes except for
|
|
* register direct, absolute, and immediate modes. However, it does
|
|
* not take care of predecrement/postincrement of register content.
|
|
* Returns a signal value (0 == no error).
|
|
*/
|
|
static int
|
|
calc_ea(struct insn_ea *ea, char *ptr, char **eaddr)
|
|
/* ptr: base address (usually a register content) */
|
|
/* eaddr: pointer to result pointer */
|
|
{
|
|
int data, word;
|
|
|
|
DPRINTF(("%s: reg indirect (reg) = %p\n", __func__, ptr));
|
|
|
|
if (ea->ea_flags & EA_OFFSET) {
|
|
/* apply the signed offset */
|
|
DPRINTF(("%s: offset %d\n", __func__, ea->ea_offset));
|
|
ptr += ea->ea_offset;
|
|
} else if (ea->ea_flags & EA_INDEXED) {
|
|
DPRINTF(("%s: indexed mode\n", __func__));
|
|
|
|
if (ea->ea_flags & EA_BASE_SUPPRSS) {
|
|
/* base register is suppressed */
|
|
ptr = (char *)ea->ea_basedisp;
|
|
} else {
|
|
ptr += ea->ea_basedisp;
|
|
}
|
|
|
|
if (ea->ea_flags & EA_MEM_INDIR) {
|
|
DPRINTF(("%s: mem indir mode: basedisp=%08x, "
|
|
"outerdisp=%08x\n",
|
|
__func__, ea->ea_basedisp, ea->ea_outerdisp));
|
|
DPRINTF(("%s: addr fetched from %p\n", __func__, ptr));
|
|
/* memory indirect modes */
|
|
word = fusword(ptr);
|
|
if (word < 0)
|
|
return SIGSEGV;
|
|
word <<= 16;
|
|
data = fusword(ptr + 2);
|
|
if (data < 0)
|
|
return SIGSEGV;
|
|
word |= data;
|
|
DPRINTF(("%s: fetched ptr 0x%08x\n", __func__, word));
|
|
ptr = (char *)word + ea->ea_outerdisp;
|
|
}
|
|
}
|
|
|
|
*eaddr = ptr;
|
|
|
|
return 0;
|
|
}
|