232 lines
7.0 KiB
C
232 lines
7.0 KiB
C
/* $NetBSD: psl.h,v 1.11 1996/03/31 22:20:14 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)psl.h 8.1 (Berkeley) 6/11/93
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*/
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#ifndef PSR_IMPL
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/*
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* SPARC Process Status Register (in psl.h for hysterical raisins).
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*
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* The picture in the Sun manuals looks like this:
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* 1 1
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* 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0
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* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
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* | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP |
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* | | |n z v c| |C|F| | |S|T| |
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* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
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*/
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#define PSR_IMPL 0xf0000000 /* implementation */
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#define PSR_VER 0x0f000000 /* version */
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#define PSR_ICC 0x00f00000 /* integer condition codes */
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#define PSR_N 0x00800000 /* negative */
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#define PSR_Z 0x00400000 /* zero */
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#define PSR_O 0x00200000 /* overflow */
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#define PSR_C 0x00100000 /* carry */
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#define PSR_EC 0x00002000 /* coprocessor enable */
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#define PSR_EF 0x00001000 /* FP enable */
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#define PSR_PIL 0x00000f00 /* interrupt level */
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#define PSR_S 0x00000080 /* supervisor (kernel) mode */
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#define PSR_PS 0x00000040 /* previous supervisor mode (traps) */
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#define PSR_ET 0x00000020 /* trap enable */
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#define PSR_CWP 0x0000001f /* current window pointer */
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#define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET"
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#define PIL_CLOCK 10
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#if defined(_KERNEL) && !defined(_LOCORE)
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static __inline int getpsr __P((void));
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static __inline void setpsr __P((int));
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static __inline int spl0 __P((void));
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static __inline int splhigh __P((void));
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static __inline void splx __P((int));
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/*
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* GCC pseudo-functions for manipulating PSR (primarily PIL field).
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*/
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static __inline int getpsr()
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{
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int psr;
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__asm __volatile("rd %%psr,%0" : "=r" (psr));
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return (psr);
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}
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static __inline void setpsr(newpsr)
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int newpsr;
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{
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__asm __volatile("wr %0,0,%%psr" : : "r" (newpsr));
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__asm __volatile("nop");
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__asm __volatile("nop");
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__asm __volatile("nop");
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}
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static __inline int spl0()
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{
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int psr, oldipl;
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/*
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* wrpsr xors two values: we choose old psr and old ipl here,
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* which gives us the same value as the old psr but with all
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* the old PIL bits turned off.
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*/
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__asm __volatile("rd %%psr,%0" : "=r" (psr));
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oldipl = psr & PSR_PIL;
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__asm __volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
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/*
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* Three instructions must execute before we can depend
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* on the bits to be changed.
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*/
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__asm __volatile("nop; nop; nop");
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return (oldipl);
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}
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/*
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* PIL 1 through 14 can use this macro.
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* (spl0 and splhigh are special since they put all 0s or all 1s
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* into the ipl field.)
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*/
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#define SPL(name, newipl) \
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static __inline int name __P((void)); \
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static __inline int name() \
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{ \
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int psr, oldipl; \
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__asm __volatile("rd %%psr,%0" : "=r" (psr)); \
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oldipl = psr & PSR_PIL; \
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psr &= ~oldipl; \
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__asm __volatile("wr %0,%1,%%psr" : : \
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"r" (psr), "n" ((newipl) << 8)); \
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__asm __volatile("nop; nop; nop"); \
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return (oldipl); \
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}
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/* A non-priority-decreasing version of SPL */
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#define SPLHOLD(name, newipl) \
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static __inline int name __P((void)); \
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static __inline int name() \
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{ \
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int psr, oldipl; \
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__asm __volatile("rd %%psr,%0" : "=r" (psr)); \
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oldipl = psr & PSR_PIL; \
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if ((newipl << 8) <= oldipl) \
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return oldipl; \
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psr &= ~oldipl; \
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__asm __volatile("wr %0,%1,%%psr" : : \
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"r" (psr), "n" ((newipl) << 8)); \
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__asm __volatile("nop; nop; nop"); \
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return (oldipl); \
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}
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SPL(splsoftint, 1)
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#define splsoftclock splsoftint
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#define splsoftnet splsoftint
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/* audio software interrupts are at software level 4 */
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#define PIL_AUSOFT 4
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SPL(splausoft, PIL_AUSOFT)
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/* floppy software interrupts are at software level 4 too */
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#define PIL_FDSOFT 4
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SPL(splfdsoft, PIL_FDSOFT)
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/* Block devices */
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SPL(splbio, 5)
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/* network hardware interrupts are at level 6 */
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#define PIL_NET 6
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SPL(splnet, PIL_NET)
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/* tty input runs at software level 6 */
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#define PIL_TTY 6
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SPL(spltty, PIL_TTY)
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/*
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* Memory allocation (must be as high as highest network, tty, or disk device)
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*/
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SPL(splimp, 7)
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SPLHOLD(splpmap, 7)
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SPL(splclock, PIL_CLOCK)
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/* fd hardware interrupts are at level 11 */
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SPL(splfd, 11)
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/* zs hardware interrupts are at level 12 */
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SPL(splzs, 12)
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/* audio hardware interrupts are at level 13 */
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SPL(splaudio, 13)
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/* second sparc timer interrupts at level 14 */
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SPL(splstatclock, 14)
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static __inline int splhigh()
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{
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int psr, oldipl;
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__asm __volatile("rd %%psr,%0" : "=r" (psr));
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__asm __volatile("wr %0,0,%%psr" : : "r" (psr | PSR_PIL));
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__asm __volatile("and %1,%2,%0; nop; nop" : "=r" (oldipl) : \
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"r" (psr), "n" (PSR_PIL));
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return (oldipl);
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}
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/* splx does not have a return value */
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static __inline void splx(newipl)
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int newipl;
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{
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int psr;
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__asm __volatile("rd %%psr,%0" : "=r" (psr));
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__asm __volatile("wr %0,%1,%%psr" : : \
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"r" (psr & ~PSR_PIL), "rn" (newipl));
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__asm __volatile("nop; nop; nop");
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}
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#endif /* KERNEL && !_LOCORE */
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#endif /* PSR_IMPL */
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