451 lines
15 KiB
C
451 lines
15 KiB
C
/* $NetBSD: pmap.h,v 1.64 2003/04/09 18:22:14 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994,1995 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM32_PMAP_H_
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#define _ARM32_PMAP_H_
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#ifdef _KERNEL
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#include <arm/cpuconf.h>
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#include <arm/cpufunc.h>
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#include <arm/arm32/pte.h>
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#include <uvm/uvm_object.h>
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/*
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* a pmap describes a processes' 4GB virtual address space. this
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* virtual address space can be broken up into 4096 1MB regions which
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* are described by L1 PTEs in the L1 table.
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*
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* There is a line drawn at KERNEL_BASE. Everything below that line
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* changes when the VM context is switched. Everything above that line
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* is the same no matter which VM context is running. This is achieved
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* by making the L1 PTEs for those slots above KERNEL_BASE reference
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* kernel L2 tables.
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*
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* The L2 tables are mapped linearly starting at PTE_BASE. PTE_BASE
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* is below KERNEL_BASE, which means that the current process's PTEs
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* are always available starting at PTE_BASE. Another region of KVA
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* above KERNEL_BASE, APTE_BASE, is reserved for mapping in the PTEs
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* of another process, should we need to manipulate them.
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*
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* The basic layout of the virtual address space thus looks like this:
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*
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* 0xffffffff
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* .
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* .
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* .
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* KERNEL_BASE
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* --------------------
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* PTE_BASE
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* .
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* .
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* .
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* 0x00000000
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*/
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/*
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* The pmap structure itself.
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*/
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struct pmap {
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struct uvm_object pm_obj; /* uvm_object */
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#define pm_lock pm_obj.vmobjlock
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LIST_ENTRY(pmap) pm_list; /* list (lck by pm_list lock) */
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pd_entry_t *pm_pdir; /* KVA of page directory */
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struct l1pt *pm_l1pt; /* L1 table metadata */
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paddr_t pm_pptpt; /* PA of pt's page table */
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vaddr_t pm_vptpt; /* VA of pt's page table */
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struct pmap_statistics pm_stats; /* pmap statistics */
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struct vm_page *pm_ptphint; /* recently used PT */
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};
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typedef struct pmap *pmap_t;
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/*
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* Physical / virtual address structure. In a number of places (particularly
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* during bootstrapping) we need to keep track of the physical and virtual
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* addresses of various pages
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*/
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typedef struct pv_addr {
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SLIST_ENTRY(pv_addr) pv_list;
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paddr_t pv_pa;
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vaddr_t pv_va;
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} pv_addr_t;
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/*
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* Determine various modes for PTEs (user vs. kernel, cacheable
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* vs. non-cacheable).
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*/
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#define PTE_KERNEL 0
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#define PTE_USER 1
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#define PTE_NOCACHE 0
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#define PTE_CACHE 1
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/*
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* Flags that indicate attributes of pages or mappings of pages.
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*
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* The PVF_MOD and PVF_REF flags are stored in the mdpage for each
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* page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
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* pv_entry's for each page. They live in the same "namespace" so
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* that we can clear multiple attributes at a time.
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*
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* Note the "non-cacheable" flag generally means the page has
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* multiple mappings in a given address space.
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*/
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#define PVF_MOD 0x01 /* page is modified */
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#define PVF_REF 0x02 /* page is referenced */
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#define PVF_WIRED 0x04 /* mapping is wired */
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#define PVF_WRITE 0x08 /* mapping is writable */
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#define PVF_EXEC 0x10 /* mapping is executable */
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#define PVF_NC 0x20 /* mapping is non-cacheable */
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/*
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* Commonly referenced structures
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*/
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extern struct pmap kernel_pmap_store;
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extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */
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/*
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* Macros that we need to export
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*/
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#define pmap_kernel() (&kernel_pmap_store)
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#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
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#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
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#define pmap_is_modified(pg) \
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(((pg)->mdpage.pvh_attrs & PVF_MOD) != 0)
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#define pmap_is_referenced(pg) \
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(((pg)->mdpage.pvh_attrs & PVF_REF) != 0)
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#define pmap_copy(dp, sp, da, l, sa) /* nothing */
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/* ARGSUSED */
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static __inline void
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pmap_remove_all(struct pmap *pmap)
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{
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/* Nothing. */
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}
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#define pmap_phys_address(ppn) (arm_ptob((ppn)))
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/*
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* Functions that we need to export
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*/
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void pmap_procwr(struct proc *, vaddr_t, int);
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#define PMAP_NEED_PROCWR
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#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */
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/* Functions we use internally. */
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void pmap_bootstrap(pd_entry_t *, pv_addr_t);
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void pmap_debug(int);
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int pmap_handled_emulation(struct pmap *, vaddr_t);
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int pmap_modified_emulation(struct pmap *, vaddr_t);
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void pmap_postinit(void);
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void vector_page_setprot(int);
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/* Bootstrapping routines. */
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void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int);
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void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int);
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vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int);
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void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *);
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/*
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* Special page zero routine for use by the idle loop (no cache cleans).
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*/
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boolean_t pmap_pageidlezero __P((paddr_t));
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#define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa))
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/*
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* The current top of kernel VM
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*/
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extern vaddr_t pmap_curmaxkvaddr;
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/*
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* Useful macros and constants
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*/
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/*
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* While the ARM MMU's L1 descriptors describe a 1M "section", each
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* one pointing to a 1K L2 table, NetBSD's VM system allocates the
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* page tables in 4K chunks, and thus we describe 4M "super sections".
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*
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* We'll lift terminology from another architecture and refer to this as
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* the "page directory" size.
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*/
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#define PD_SIZE (L1_S_SIZE * 4) /* 4M */
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#define PD_OFFSET (PD_SIZE - 1)
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#define PD_FRAME (~PD_OFFSET)
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#define PD_SHIFT 22
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/* Virtual address to page table entry */
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#define vtopte(va) \
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(((pt_entry_t *)PTE_BASE) + arm_btop((vaddr_t) (va)))
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/* Virtual address to physical address */
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#define vtophys(va) \
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((*vtopte(va) & L2_S_FRAME) | ((vaddr_t) (va) & L2_S_OFFSET))
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#define PTE_SYNC(pte) \
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cpu_dcache_wb_range((vaddr_t)(pte), sizeof(pt_entry_t))
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#define PTE_FLUSH(pte) \
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cpu_dcache_wbinv_range((vaddr_t)(pte), sizeof(pt_entry_t))
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#define PTE_SYNC_RANGE(pte, cnt) \
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cpu_dcache_wb_range((vaddr_t)(pte), (cnt) << 2) /* * sizeof(...) */
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#define PTE_FLUSH_RANGE(pte, cnt) \
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cpu_dcache_wbinv_range((vaddr_t)(pte), (cnt) << 2) /* * sizeof(...) */
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#define l1pte_valid(pde) ((pde) != 0)
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#define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
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#define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
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#define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
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#define l2pte_valid(pte) ((pte) != 0)
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#define l2pte_pa(pte) ((pte) & L2_S_FRAME)
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/* L1 and L2 page table macros */
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#define pmap_pdei(v) ((v & L1_S_FRAME) >> L1_S_SHIFT)
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#define pmap_pde(m, v) (&((m)->pm_pdir[pmap_pdei(v)]))
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#define pmap_pde_v(pde) l1pte_valid(*(pde))
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#define pmap_pde_section(pde) l1pte_section_p(*(pde))
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#define pmap_pde_page(pde) l1pte_page_p(*(pde))
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#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde))
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#define pmap_pte_v(pte) l2pte_valid(*(pte))
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#define pmap_pte_pa(pte) l2pte_pa(*(pte))
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/* Size of the kernel part of the L1 page table */
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#define KERNEL_PD_SIZE \
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(L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t))
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/************************* ARM MMU configuration *****************************/
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#if ARM_MMU_GENERIC == 1
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void pmap_copy_page_generic(paddr_t, paddr_t);
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void pmap_zero_page_generic(paddr_t);
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void pmap_pte_init_generic(void);
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#if defined(CPU_ARM9)
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void pmap_pte_init_arm9(void);
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#endif /* CPU_ARM9 */
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#endif /* ARM_MMU_GENERIC == 1 */
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#if ARM_MMU_XSCALE == 1
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void pmap_copy_page_xscale(paddr_t, paddr_t);
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void pmap_zero_page_xscale(paddr_t);
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void pmap_pte_init_xscale(void);
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void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t);
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#endif /* ARM_MMU_XSCALE == 1 */
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extern pt_entry_t pte_l1_s_cache_mode;
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extern pt_entry_t pte_l1_s_cache_mask;
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extern pt_entry_t pte_l2_l_cache_mode;
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extern pt_entry_t pte_l2_l_cache_mask;
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extern pt_entry_t pte_l2_s_cache_mode;
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extern pt_entry_t pte_l2_s_cache_mask;
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extern pt_entry_t pte_l2_s_prot_u;
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extern pt_entry_t pte_l2_s_prot_w;
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extern pt_entry_t pte_l2_s_prot_mask;
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extern pt_entry_t pte_l1_s_proto;
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extern pt_entry_t pte_l1_c_proto;
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extern pt_entry_t pte_l2_s_proto;
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extern void (*pmap_copy_page_func)(paddr_t, paddr_t);
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extern void (*pmap_zero_page_func)(paddr_t);
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/*****************************************************************************/
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/*
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* tell MI code that the cache is virtually-indexed *and* virtually-tagged.
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*/
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#define PMAP_CACHE_VIVT
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/*
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* These macros define the various bit masks in the PTE.
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*
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* We use these macros since we use different bits on different processor
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* models.
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*/
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#define L1_S_PROT_U (L1_S_AP(AP_U))
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#define L1_S_PROT_W (L1_S_AP(AP_W))
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#define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W)
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#define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
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#define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X))
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#define L2_L_PROT_U (L2_AP(AP_U))
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#define L2_L_PROT_W (L2_AP(AP_W))
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#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W)
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#define L2_L_CACHE_MASK_generic (L2_B|L2_C)
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#define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X))
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#define L2_S_PROT_U_generic (L2_AP(AP_U))
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#define L2_S_PROT_W_generic (L2_AP(AP_W))
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#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W)
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#define L2_S_PROT_U_xscale (L2_AP0(AP_U))
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#define L2_S_PROT_W_xscale (L2_AP0(AP_W))
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#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W)
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#define L2_S_CACHE_MASK_generic (L2_B|L2_C)
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#define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X))
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#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP)
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#define L1_S_PROTO_xscale (L1_TYPE_S)
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#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2)
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#define L1_C_PROTO_xscale (L1_TYPE_C)
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#define L2_L_PROTO (L2_TYPE_L)
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#define L2_S_PROTO_generic (L2_TYPE_S)
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#define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS)
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/*
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* User-visible names for the ones that vary with MMU class.
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*/
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#if ARM_NMMUS > 1
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/* More than one MMU class configured; use variables. */
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#define L2_S_PROT_U pte_l2_s_prot_u
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#define L2_S_PROT_W pte_l2_s_prot_w
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#define L2_S_PROT_MASK pte_l2_s_prot_mask
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#define L1_S_CACHE_MASK pte_l1_s_cache_mask
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#define L2_L_CACHE_MASK pte_l2_l_cache_mask
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#define L2_S_CACHE_MASK pte_l2_s_cache_mask
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#define L1_S_PROTO pte_l1_s_proto
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#define L1_C_PROTO pte_l1_c_proto
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#define L2_S_PROTO pte_l2_s_proto
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#define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d))
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#define pmap_zero_page(d) (*pmap_zero_page_func)((d))
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#elif ARM_MMU_GENERIC == 1
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#define L2_S_PROT_U L2_S_PROT_U_generic
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#define L2_S_PROT_W L2_S_PROT_W_generic
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#define L2_S_PROT_MASK L2_S_PROT_MASK_generic
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#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic
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#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic
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#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic
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#define L1_S_PROTO L1_S_PROTO_generic
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#define L1_C_PROTO L1_C_PROTO_generic
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#define L2_S_PROTO L2_S_PROTO_generic
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#define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d))
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#define pmap_zero_page(d) pmap_zero_page_generic((d))
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#elif ARM_MMU_XSCALE == 1
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#define L2_S_PROT_U L2_S_PROT_U_xscale
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#define L2_S_PROT_W L2_S_PROT_W_xscale
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#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale
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#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale
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#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale
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#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale
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#define L1_S_PROTO L1_S_PROTO_xscale
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#define L1_C_PROTO L1_C_PROTO_xscale
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#define L2_S_PROTO L2_S_PROTO_xscale
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#define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d))
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#define pmap_zero_page(d) pmap_zero_page_xscale((d))
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#endif /* ARM_NMMUS > 1 */
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/*
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* These macros return various bits based on kernel/user and protection.
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* Note that the compiler will usually fold these at compile time.
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*/
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#define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0))
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#define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0))
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#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
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/*
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* Hooks for the pool allocator.
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*/
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#define POOL_VTOPHYS(va) vtophys((vaddr_t) (va))
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#endif /* _KERNEL */
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#endif /* _ARM32_PMAP_H_ */
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