149 lines
4.6 KiB
C
149 lines
4.6 KiB
C
/* $NetBSD: intr.h,v 1.18 2009/04/13 09:37:50 he Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jonathan Stone for
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* the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACHINE_INTR_H_
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#define _MACHINE_INTR_H_
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#define IPL_NONE 0 /* disable only this interrupt */
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#define IPL_SOFTCLOCK 1 /* generic software interrupts */
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#define IPL_SOFTBIO 1 /* clock software interrupts */
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#define IPL_SOFTNET 2 /* network software interrupts */
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#define IPL_SOFTSERIAL 2 /* serial software interrupts */
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#define IPL_VM 3
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#define IPL_SCHED 4
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#define IPL_HIGH 4 /* disable all interrupts */
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#define IPL_N 5
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#ifdef _KERNEL
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#ifndef _LOCORE
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#include <sys/types.h>
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#include <sys/evcnt.h>
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#include <sys/queue.h>
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#include <mips/locore.h>
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/*
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* software simulated interrupt
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*/
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#define setsoft(x) do { \
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extern u_int ssir; \
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int _s; \
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\
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_s = splhigh(); \
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ssir |= 1 << (x); \
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_setsoftintr(MIPS_SOFT_INT_MASK_1); \
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splx(_s); \
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} while (0)
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/*
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* nesting interrupt masks.
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*/
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#define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0
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#define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
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#define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
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#define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
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#define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
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#define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
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#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
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#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
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#define spl0() (void)_spllower(0)
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#define splx(s) (void)_splset(s)
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#define splvm() _splraise(MIPS_INT_MASK_SPL2)
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#define splsched() _splraise(MIPS_INT_MASK_SPL2)
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#define splhigh() _splraise(MIPS_INT_MASK_SPL2)
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#define splsoftclock() _splraise(MIPS_INT_MASK_SPL_SOFT0)
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#define splsoftbio() _splraise(MIPS_INT_MASK_SPL_SOFT0)
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#define splsoftnet() _splraise(MIPS_INT_MASK_SPL_SOFT1)
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#define splsoftserial() _splraise(MIPS_INT_MASK_SPL_SOFT1)
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typedef int ipl_t;
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typedef struct {
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int _sr;
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} ipl_cookie_t;
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ipl_cookie_t makeiplcookie(ipl_t ipl);
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static inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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return _splraise(icookie._sr);
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}
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struct mipsco_intrhand {
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LIST_ENTRY(mipsco_intrhand)
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ih_q;
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int (*ih_fun)(void *);
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void *ih_arg;
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struct mipsco_intr *ih_intrhead;
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int ih_pending;
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};
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struct mipsco_intr {
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LIST_HEAD(,mipsco_intrhand)
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intr_q;
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struct evcnt ih_evcnt;
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unsigned long intr_siq;
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};
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extern struct mipsco_intrhand intrtab[];
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#define SYS_INTR_LEVEL0 0
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#define SYS_INTR_LEVEL1 1
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#define SYS_INTR_LEVEL2 2
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#define SYS_INTR_LEVEL3 3
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#define SYS_INTR_LEVEL4 4
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#define SYS_INTR_LEVEL5 5
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#define SYS_INTR_SCSI 6
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#define SYS_INTR_TIMER 7
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#define SYS_INTR_ETHER 8
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#define SYS_INTR_SCC0 9
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#define SYS_INTR_FDC 10
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#define SYS_INTR_ATBUS 11
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#define MAX_INTR_COOKIES 16
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#define CALL_INTR(lev) ((*intrtab[lev].ih_fun)(intrtab[lev].ih_arg))
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#endif /* !_LOCORE */
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#endif /* _KERNEL */
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#endif /* _MACHINE_INTR_H_ */
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