227 lines
8.1 KiB
C
227 lines
8.1 KiB
C
/* $NetBSD: sbd_tr2.h,v 1.2 2008/04/28 20:23:18 martin Exp $ */
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SBD_TR2_PRIVATE
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#error "Don't inlucde this file except for TR2 implemetation"
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#endif /* !_SBD_TR2_PRIVATE */
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#ifndef _EWS4800MIPS_SBD_TR2_H_
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#define _EWS4800MIPS_SBD_TR2_H_
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/*
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* EWS4800/350 (TR2) specific system board definition
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*/
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/* ROM */
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#define TR2_ROM_FONT_ADDR 0xbfc0ec00
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#define TR2_ROM_FONT_SIZE ((0x7f - 0x20) * 24 * sizeof(int16_t))
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#define TR2_ROM_KEYMAP_NORMAL ((uint8_t *)0xbfc12d6c)
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#define TR2_ROM_KEYMAP_SHIFTED ((uint8_t *)0xbfc12dec)
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#define TR2_ROM_KEYMAP_CONTROL ((uint8_t *)0xbfc12e6c)
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#define TR2_ROM_KEYMAP_CAPSLOCK ((uint8_t *)0xbfc12eec)
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#define TR2_ROM_KBD_TYPE 0xbfc0fe04 /* [d0 00 00 01] used by kbmskbreset. */
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#define TR2_ROM_PUTC ((void (*)(int, int, int))0xbfc04f28)
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#define TR2_ROM_GETC ((int (*)(void))0xbfc11fa0)
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/* System board I/O devices */
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#define TR2_PICNIC_ADDR 0xbb000000
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#define TR2_KBMS_ADDR 0xbb010000
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#define TR2_SIO_ADDR 0xbb011000
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#define TR2_NVSRAM_ADDR 0xbb020000
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#define TR2_NVSRAM_SIZE 0x00004000
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#define TR2_FDC_ADDR 0xbb030000
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#define TR2_LPT_ADDR 0xbb040000
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#define TR2_SCSI_ADDR 0xbb050000
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#define TR2_ETHER_ADDR 0xbb060000
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#define TR2_MEMC_ADDR 0xbfa00000
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#define TR2_NABI_ADDR 0xbfb00000
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#define TR2_GAFB_ADDR 0xf0000000
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#define TR2_GAFB_SIZE 0x08000000
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#define TR2_GACTRL_ADDR 0xf5f00000
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#define TR2_GACTRL_SIZE 0x1000
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#define SOFTRESET_REG ((volatile uint32_t *)0xbfb00000)
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#define POWEROFF_REG ((volatile uint8_t *)0xbb004000)
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#define UPS_STATUS_REG ((volatile uint8_t *)0xbb004008) /* mask 0xffffffbb, 0x4 */
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#define LED_TF_REG ((volatile uint8_t *)0xbb006000) /* 0/1 (Red)*/
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#define TF_ERROR_CODE ((volatile uint8_t *)0xbb006004) /* 1-255 */
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#define BUZZER_REG ((volatile uint8_t *)0xbb007000)
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/* NABI */
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#define NABI0_CTRL_REG ((volatile uint32_t *)0xbfb00000)
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#define NABI1_CTRL_REG ((volatile uint32_t *)0xbfb00004)
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#define NABI2_CTRL_REG ((volatile uint32_t *)0xbfb00008)
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#define NABI0_INTR_REG ((volatile uint32_t *)0xbfb00010)
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#define NABI1_INTR_REG ((volatile uint32_t *)0xbfb00018) /* VME */
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#define NABI2_INTR_REG ((volatile uint32_t *)0xbfb0001c)
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/*
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* PICNIC (interrupt controller)
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*/
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#define PICNIC_INT0_STATUS_REG ((volatile uint8_t *)0xbb000000)
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#define PICNIC_INT2_STATUS_REG ((volatile uint8_t *)0xbb000004)
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#define PICNIC_INT4_STATUS_REG ((volatile uint8_t *)0xbb000008)
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#define PICNIC_INT5_STATUS_REG ((volatile uint8_t *)0xbb000010)
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#define PICNIC_NMI_REG ((volatile uint8_t *)0xbb000014)
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#define PICNIC_INT0_MASK_REG ((volatile uint8_t *)0xbb001000)
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#define PICNIC_INT2_MASK_REG ((volatile uint8_t *)0xbb001004)
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#define PICNIC_INT4_MASK_REG ((volatile uint8_t *)0xbb001008)
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#define PICNIC_INT5_MASK_REG ((volatile uint8_t *)0xbb001010)
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/* Interrupt source */
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#define PICNIC_INT_FDDLPT 0x80
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#define PICNIC_INT_ETHER 0x40
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#define PICNIC_INT_SCSI 0x20
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#define PICNIC_INT_SERIAL 0x04
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#define PICNIC_INT_KBMS 0x01
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#define PICNIC_INT_CLOCK 0x01
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/*
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* 76543210
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* ||| | +-- keyboard, mouse
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* ||| +-----serial
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* ||+--------SCSI
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* |+---------ether
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* +----------FDC, printer
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*0xbb00 UX IPL mips int
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* 1000 0x80 0x00 7 INT0
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* 1004 0x60 0x00 65 INT2
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* 1008 0x05 0x00 2 0 INT4
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* 1010 0x01 0x01 0 Clock INT5
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*/
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/* SIO0 Z85C30 */
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#define KBD_STATUS ((volatile uint8_t *)0xbb010000)
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#define KBD_DATA ((volatile uint8_t *)0xbb010004)
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#define MOUSE_STATUS ((volatile uint8_t *)0xbb010008)
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#define MOUSE_DATA ((volatile uint8_t *)0xbb01000c)
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/* SIO1 Z85C30 */
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#define SIOA_STATUS ((volatile uint8_t *)0xbb011008)
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#define SIOA_RDATA ((volatile uint8_t *)0xbb01100c)
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#define SIOB_STATUS ((volatile uint8_t *)0xbb011000)
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#define SIOB_RDATA ((volatile uint8_t *)0xbb011004)
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/* ETHER i82589 */
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/* read operation invokes channel attention. */
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#define ETHER_SETADDR_REG ((volatile uint32_t *)0xbb060000)
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/* DCC (DMA controler. Parallel port and FDD use this.) */
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struct DCC {
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uint32_t addr; /* DMA address */
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uint32_t cnt; /* transfer count */
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uint32_t ctrl; /* DMA status/command */
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uint32_t drm;
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} __attribute__((__packed__));
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/* FDD uPD72065 (80track ready) */
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#define FDC_DMA ((volatile struct DCC *)0xbb030000)
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#define FDC_STATUS ((volatile uint8_t *)0xbb030010)
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#define FDC_DATA ((volatile uint8_t *)0xbb030014)
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/* LPT */
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#define LPT_DMA (((volatile struct DCC *)0xbb040000)
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#define LPT_COUNT ((volatile uint8_t *)0xbb040010)
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#define LPT_STRR ((volatile uint8_t *)0xbb040011)
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/* NVSRAM MK48T08B-15 (word aligned byte access) */
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/* 0, 4, 8, c */
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#define NVSRAM_SIGNATURE 0xbb020000
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/* 10, 14 18 1c */
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#define NVSRAM_MACHINEID 0xbb020010
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#define NVSRAM_ETHERADDR ((uint8_t *)0xbb021008)
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/* 2000, 2004, 2008, 200c */
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#define NVSRAM_CDUMP_ADDR ((uint8_t *)0xbb022000)
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#define NVSRAM_DUMPDEV_1XXX 0xbb022020
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#define NVSRAM_DUMPDEV_2XXX 0xbb022040
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/* 2050, 2054, 2058, 205c */
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#define NVSRAM_TF_SCRATCH_ADDR 0xbb022050
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#if 0
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/* kbd */
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#define NVSRAM_KBD??? 0xbb0220a0 /* 0x90 */
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#endif
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#define NVSRAM_TF_TESTDATA1 0xbb023000
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#define NVSRAM_TF_TESTDATA2 0xbb023004
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#define NVSRAM_KEYMAP ((uint8_t *)0xbb023014) /* scratch */
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#define NVSRAM_TF_PROGRESS ((uint8_t *)0xbb02301c)
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#define NVSRAM_BEV_ROM 32 /* Exception from ROM routine */
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#define NVSRAM_KBDCONNECT ((uint8_t *)0xbb023010)
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#define HAS_KBD() (*NVSRAM_KBDCONNECT != 255)
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#define NVSRAM_CONSTYPE ((uint8_t *)0xbb023020)
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#define IS_FBCONS() (*NVSRAM_CONSTYPE == 0)
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#define NVSRAM_GA 0xbb023008
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#define HAS_GA 0
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#define NVSRAM_TF_RESULT_HI 0xbb023024
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#define NVSRAM_TF_RESULT_LO 0xbb023028
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#define NVSRAM_IPLMODE ((uint8_t *)0xbb02302c)
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/*
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* 0: Normal mode
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* 1: ERROR continue mode
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* 2: Details mode
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* 3: LOOP mode
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*/
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#define NVSRAM_BOOTDEV ((uint8_t *)0xbb023030)
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#define NVSRAM_BOOTUNIT ((uint8_t *)0xbb023034)
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/* V1 is memory area information */
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#define NVSRAM_1STBOOT_ARG_V1_3 ((uint8_t *)0xbb023048) /* 24-31 */
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#define NVSRAM_1STBOOT_ARG_V1_2 ((uint8_t *)0xbb02304c) /* 16-23 */
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#define NVSRAM_1STBOOT_ARG_V1_1 ((uint8_t *)0xbb023050) /* 8 -15 */
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#define NVSRAM_1STBOOT_ARG_V1_0 ((uint8_t *)0xbb023054) /* 0 - 7 */
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#define NVSRAM_1STBOOT_ARG_V0 ((uint8_t *)0xbb023058)
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#define NVSRAM_SIMM_3_2 ((uint8_t *)0xbb023050)
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#define NVSRAM_SIMM_1_0 ((uint8_t *)0xbb023054)
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#define SIMM_16M 0x1
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#define SIMM_32M 0x2
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#define NVSRAM_RTCADDR ((uint8_t *)0xbb027fe0)
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/* Graphic adapter */
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#include <machine/gareg.h>
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/*
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* VME (350/380)
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*/
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#define VME_ADDR 0xf8000000
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#define VME_32_ADDR 0xf8000000
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#define VME_32_SIZE 0x07000000
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#define VME_BUFFER_ADDR 0xff000000
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#define VME_BUFFER_SIZE 0x00800000
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#define VME_24_ADDR 0xff800000
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#define VME_24_SIZE 0x007f0000
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#define VME_SHORTIO_ADDR 0xffff0000
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#define VME_SHORTIO_SIZE 0x00010000
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#endif /* !_EWS4800MIPS_SBD_TR2_H_ */
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