159 lines
6.1 KiB
C
159 lines
6.1 KiB
C
/* $NetBSD: pciide_hpt_reg.h,v 1.12 2005/02/27 00:27:33 perry Exp $ */
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/*
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* Copyright (c) 2000 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Register definitions for the Highpoint HPT366 UDMA/66 * and HPT370 UDMA/100
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* PCI IDE controller.
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*
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* The HPT366 has 2 PCI IDE functions, each of them has only one channel.
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* The HPT370 has the 2 channels on the same PCI IDE function.
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*/
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/*
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* The HPT366 and HPT370 have the save vendor/device ID but not the
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* same revision
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*/
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#define HPT366_REV 0x01
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#define HPT370_REV 0x03
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#define HPT370A_REV 0x04
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#define HPT372_REV 0x05
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#define HPT374_REV 0x07
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#define HPT_IDETIM(chan, drive) (0x40 + ((drive) * 4) + ((chan) * 8))
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#define HPT_IDETIM_BUFEN 0x80000000
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#define HPT_IDETIM_MSTEN 0x40000000
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#define HPT_IDETIM_DMAEN 0x20000000
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#define HPT_IDETIM_UDMAEN 0x10000000
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#define HPT366_CTRL1 0x50
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#define HPT366_CTRL1_BLKDIS(chan) (0x40 << (chan))
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#define HPT366_CTRL1_CHANEN(chan) (0x10 << (chan))
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#define HPT366_CTRL1_CLRBUF(chan) (0x04 << (chan))
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#define HPT366_CTRL1_LEG(chan) (0x01 << (chan))
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#define HPT366_CTRL2 0x51
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#define HPT366_CTRL2_FASTIRQ 0x80
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#define HPT366_CTRL2_HOLDIRQ(chan) (0x20 << (chan))
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#define HPT366_CTRL2_SGEN 0x10
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#define HPT366_CTRL2_CLEARFIFO(chan) (0x04 << (chan))
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#define HPT366_CTRL2_CLEARBMSM 0x02
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#define HPT366_CTRL2_CLEARSG 0x01
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#define HPT366_CTRL3(chan) (0x52 + ((chan) * 4))
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#define HPT366_CTRL3_PDMA 0x8000
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#define HPT366_CTRL3_BP 0x4000
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#define HPT366_CTRL3_FASTIRQ_OFFSET 9
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#define HPT366_CTRL3_FASTIRQ_MASK 0x3
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#define HPT370_CTRL1(chan) (0x50 + ((chan) * 4))
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#define HPT370_CTRL1_CLRSG 0x80
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#define HPT370_CTRL1_READF 0x40
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#define HPT370_CTRL1_CLRST 0x20
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#define HPT370_CTRL1_CLRSGC 0x10
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#define HPT370_CTRL1_BLKDIS 0x08
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#define HPT370_CTRL1_EN 0x04
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#define HPT370_CTRL1_CLRDBUF 0x02
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#define HPT370_CTRL1_LEGEN 0x01
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#define HPT370_CTRL2(chan) (0x51 + ((chan) * 4))
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#define HPT370_CTRL2_FASTIRQ 0x02
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#define HPT370_CTRL2_HIRQ 0x01
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#define HPT370_CTRL3(chan) (0x52 + ((chan) * 4))
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#define HPT370_CTRL3_HIZ 0x8000
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#define HPT370_CTRL3_BP 0x4000
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#define HPT370_CTRL3_FASTIRQ_OFFSET 9
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#define HPT370_CTRL3_FASTIRQ_MASK 0x3
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#define HPT_STAT1 0x58
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#define HPT_STAT1_IRQPOLL(chan) (0x40 << (chan)) /* 366 only */
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#define HPT_STAT1_DMARQ(chan) (0x04 << ((chan) * 3))
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#define HPT_STAT1_DMACK(chan) (0x02 << ((chan) * 3))
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#define HPT_STAT1_IORDY(chan) (0x01 << ((chan) * 3))
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#define HPT_STAT2 0x59
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#define HPT_STAT2_FLT_RST 0x40 /* 366 only */
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#define HPT_STAT2_RST(chan) (0x40 << (chan)) /* 370 only */
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#define HPT_STAT2_POLLEN(chan) (0x04 << ((chan) * 3))
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#define HPT_STAT2_IRQD1(chan) (0x02 << ((chan) * 3))
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#define HPT_STAT2_IRQD0_CH1 0x08
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#define HPT_STAT2_POLLST 0x01
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#define HPT_CSEL 0x5a
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#define HPT_CSEL_IRQDIS 0x10 /* 370 only */
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#define HPT_CSEL_PCIDIS 0x08 /* 370 only */
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#define HPT_CSEL_PCIWR 0x04 /* 370 only */
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#define HPT_CSEL_CBLID(chan) (0x01 << (1 - (chan)))
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#define HPT_SC2 0x5b
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#define HPT_SC2_OSC_OK 0x80
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#define HPT_SC2_OSC_EN 0x20
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#define HPT_SC2_ECLK 0x10
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#define HPT_SC2_BPIO 0x08
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#define HPT_SC2_DMARQW 0x04
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#define HPT_SC2_SCLK 0x02
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#define HPT_SC2_MAEN 0x01
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#define HPT370_FOUT 0x7c /* DPLL output frequency */
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static const u_int32_t hpt366_pio[] __attribute__((__unused__)) =
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{0x00d0a7aa, 0x00c8a753, 0x00c8a742, 0x00c8a731};
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static const u_int32_t hpt366_dma[] __attribute__((__unused__)) =
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{0x20c8a797, 0x20c8a742, 0x20c8a731};
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static const u_int32_t hpt366_udma[] __attribute__((__unused__)) =
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{0x10c8a731, 0x10cba731, 0x10caa731, 0x10cfa731, 0x10c9a731};
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static const u_int32_t hpt370_pio[] __attribute__((__unused__)) =
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{0x06914e8a, 0x06914e65, 0x06514e33, 0x06514e22, 0x06514e21};
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static const u_int32_t hpt370_dma[] __attribute__((__unused__)) =
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{0x26514e97, 0x26514e33, 0x26514e21};
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static const u_int32_t hpt370_udma[] __attribute__((__unused__)) =
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{0x16514e31, 0x164d4e31, 0x16494e31, 0x166d4e31, 0x16454e31,
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0x1a85f442};
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static const u_int32_t hpt372_pio[] __attribute__((__unused__)) =
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{0x0d029d5e, 0x0d029d26, 0x0c829ca6, 0x0c829c84, 0x0c829c62};
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static const u_int32_t hpt372_dma[] __attribute__((__unused__)) =
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{0x2c829d2e, 0x2c829c66, 0x2829c62};
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static const u_int32_t hpt372_udma[] __attribute__((__unused__)) =
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{0x1c829c62, 0x1c9a9c62, 0x1c929c62, 0x1c8e9c62, 0x1c8a9c62,
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0x1cae9c62, 0x1c869c62};
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static u_int32_t hpt374_pio[] __attribute__((__unused__)) =
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{0x0ac1f48a, 0x0ac1f465, 0x0a81f454, 0x0a81f443, 0x0a81f442};
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static u_int32_t hpt374_dma[] __attribute__((__unused__)) =
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{0x228082ea, 0x22808254, 0x22808242};
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static u_int32_t hpt374_udma[] __attribute__((__unused__)) =
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{0x121882ea, 0x12148254, 0x120c8242, 0x128c8242, 0x12ac8242,
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0x12848242, 0x12808242};
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