284 lines
7.3 KiB
C
284 lines
7.3 KiB
C
/* $NetBSD: mem.c,v 1.13 1995/09/26 20:16:30 phil Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1986, 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)mem.c 8.3 (Berkeley) 1/12/94
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*/
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/*
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* Memory special file
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*/
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/buf.h>
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#include <sys/systm.h>
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#include <sys/uio.h>
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#include <sys/malloc.h>
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#include <machine/cpu.h>
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#include <vm/vm.h>
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extern char *vmmap; /* poor name! */
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caddr_t zeropage;
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#ifndef NO_RTC
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int have_rtc = 1; /* For access to rtc. */
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#else
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int have_rtc = 0; /* For no rtc. */
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#endif
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#define ROM_ORIGIN 0xFFF00000 /* Mapped origin! */
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/* Do the actual reading and writing of the rtc. We have to read
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and write the entire contents at a time. rw = 0 => read,
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rw = 1 => write. */
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void rw_rtc (unsigned char *buffer, int rw)
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{
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static unsigned char magic[8] =
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{0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c};
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volatile unsigned char * const rom_p = (unsigned char *)ROM_ORIGIN;
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unsigned char *bp;
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unsigned char dummy; /* To defeat optimization */
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/* Read or write to the real time chip. Address line A0 functions as
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* data input, A2 is used as the /write signal. Accesses to the RTC
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* are always done to one of the addresses (unmapped):
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*
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* 0x10000000 - write a '0' bit
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* 0x10000001 - write a '1' bit
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* 0x10000004 - read a bit
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*
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* Data is output from the RTC using D0. To read or write time
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* information, the chip has to be activated first, to distinguish
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* clock accesses from normal ROM reads. This is done by writing,
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* bit by bit, a magic pattern to the chip. Before that, a dummy read
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* assures that the chip's pattern comparison register pointer is
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* reset. The RTC register file is always read or written wholly,
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* even if we are only interested in a part of it.
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*/
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/* Activate the real time chip */
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dummy = rom_p[4]; /* Synchronize the comparison reg. */
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for (bp=magic; bp<magic+8; bp++) {
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int i;
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for (i=0; i<8; i++)
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dummy = rom_p[ (*bp>>i) & 0x01 ];
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}
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if (rw == 0) {
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/* Read the time from the RTC. Do this even this is
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a write, since the user might have only given
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partial data and the RTC must always be written
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completely.
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*/
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for (bp=buffer; bp<buffer+8; bp++) {
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int i;
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for (i=0; i<8; i++) {
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*bp >>= 1;
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*bp |= ((rom_p[4] & 0x01) ? 0x80 : 0x00);
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}
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}
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} else {
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/* Write to the RTC */
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for (bp=buffer; bp<buffer+8; bp++) {
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int i;
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for (i=0; i<8; i++)
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dummy = rom_p[ (*bp>>i) & 0x01 ];
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}
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}
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}
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/*ARGSUSED*/
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int
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mmopen(dev, flag, mode)
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dev_t dev;
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int flag, mode;
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{
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return (0);
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}
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/*ARGSUSED*/
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int
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mmclose(dev, flag, mode)
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dev_t dev;
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int flag, mode;
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{
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return (0);
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}
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/*ARGSUSED*/
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int
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mmrw(dev, uio, flags)
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dev_t dev;
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struct uio *uio;
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int flags;
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{
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register vm_offset_t o, v;
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register int c;
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register struct iovec *iov;
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int error = 0;
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static int physlock;
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/* /dev/rtc support. */
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unsigned char buffer[8];
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if (minor(dev) == 0) {
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/* lock against other uses of shared vmmap */
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while (physlock > 0) {
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physlock++;
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error = tsleep((caddr_t)&physlock, PZERO | PCATCH,
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"mmrw", 0);
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if (error)
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return (error);
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}
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physlock = 1;
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}
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while (uio->uio_resid > 0 && error == 0) {
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iov = uio->uio_iov;
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if (iov->iov_len == 0) {
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uio->uio_iov++;
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uio->uio_iovcnt--;
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if (uio->uio_iovcnt < 0)
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panic("mmrw");
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continue;
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}
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switch (minor(dev)) {
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/* minor device 0 is physical memory */
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case 0:
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v = uio->uio_offset;
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pmap_enter(pmap_kernel(), (vm_offset_t)vmmap,
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trunc_page(v), uio->uio_rw == UIO_READ ?
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VM_PROT_READ : VM_PROT_WRITE, TRUE);
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o = uio->uio_offset & PGOFSET;
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c = min(uio->uio_resid, (int)(NBPG - o));
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error = uiomove((caddr_t)vmmap + o, c, uio);
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pmap_remove(pmap_kernel(), (vm_offset_t)vmmap,
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(vm_offset_t)vmmap + NBPG);
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continue;
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/* minor device 1 is kernel memory */
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case 1:
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v = uio->uio_offset;
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c = min(iov->iov_len, MAXPHYS);
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if (!kernacc((caddr_t)v, c,
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uio->uio_rw == UIO_READ ? B_READ : B_WRITE))
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return (EFAULT);
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error = uiomove((caddr_t)v, c, uio);
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continue;
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/* minor device 2 is EOF/RATHOLE */
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case 2:
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if (uio->uio_rw == UIO_WRITE)
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uio->uio_resid = 0;
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return (0);
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#ifdef DEV_RTC
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/* minor device 3 is the realtime clock. */
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case 3:
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if (!have_rtc)
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return (ENXIO);
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/* Calc offsets and lengths. */
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v = uio->uio_offset;
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if (v > 8)
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return (0); /* EOF */
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c = iov->iov_len;
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if (v+c > 8)
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c = 8-v;
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rw_rtc(buffer, 0); /* Read the rtc. */
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error = uiomove((caddr_t)&buffer[v], c, uio);
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if (uio->uio_rw == UIO_READ || error)
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return (error);
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rw_rtc(buffer, 1); /* Write the rtc. */
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return (error);
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#endif
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/* minor device 12 (/dev/zero) is source of nulls on read, rathole on write */
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case 12:
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if (uio->uio_rw == UIO_WRITE) {
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c = iov->iov_len;
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break;
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}
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if (zeropage == NULL) {
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zeropage = (caddr_t)
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malloc(CLBYTES, M_TEMP, M_WAITOK);
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bzero(zeropage, CLBYTES);
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}
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c = min(iov->iov_len, CLBYTES);
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error = uiomove(zeropage, c, uio);
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continue;
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default:
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return (ENXIO);
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}
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if (error)
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break;
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iov->iov_base += c;
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iov->iov_len -= c;
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uio->uio_offset += c;
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uio->uio_resid -= c;
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}
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if (minor(dev) == 0) {
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unlock:
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if (physlock > 1)
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wakeup((caddr_t)&physlock);
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physlock = 0;
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}
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return (error);
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}
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int
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mmmmap(dev, off, prot)
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dev_t dev;
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int off, prot;
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{
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return (EOPNOTSUPP);
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}
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