117 lines
4.5 KiB
C
117 lines
4.5 KiB
C
/* $NetBSD: it8368reg.h,v 1.4 2001/09/15 12:47:05 uch Exp $ */
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/*-
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* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* ITE IT8368E PCMCIA/GPIO Buffer Chip
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* http://www.ite.com/tw/mobile/it8368v07.pdf
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*/
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#define IT8368_GPIODATAOUT_REG 0x00
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#define IT8368_MFIODATAOUT_REG 0x02
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#define IT8368_GPIODIR_REG 0x04
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#define IT8368_MFIODIR_REG 0x06
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#define IT8368_MFIOSEL_REG 0x0a
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#define IT8368_GPIODATAIN_REG 0x0c
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#define IT8368_MFIODATAIN_REG 0x0e
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#define IT8368_GPIOPOSINTEN_REG 0x10
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#define IT8368_MFIOPOSINTEN_REG 0x12
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#define IT8368_GPIONEGINTEN_REG 0x14
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#define IT8368_MFIONEGINTEN_REG 0x16
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#define IT8368_GPIOPOSINTSTAT_REG 0x18
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#define IT8368_MFIOPOSINTSTAT_REG 0x1a
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#define IT8368_GPIONEGINTSTAT_REG 0x1c
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#define IT8368_MFIONEGINTSTAT_REG 0x1e
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#define IT8368_CTRL_REG 0x20
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#define IT8368_GPIO_MAX 12
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#define IT8368_MFIO_MAX 10
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#define IT8368_GPIODATAOUT_MASK 0x1fff
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#define IT8368_MFIODATAOUT_MASK 0x07ff
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#define IT8368_GPIODIR_MASK 0x1fff
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#define IT8368_MFIODIR_MASK 0x07ff
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#define IT8368_MFIOSEL_VGAEN 0x0800
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#define IT8368_MFIOSEL_MASK 0x07ff
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#define IT8368_GPIODATAIN_MASK 0x1fff
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#define IT8368_MFIODATAIN_MASK 0x07ff
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#define IT8368_GPIOPOSINTEN_MASK 0x1fff
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#define IT8368_MFIOPOSINTEN_MASK 0x07ff
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#define IT8368_GPIONEGINTEN_MASK 0x1fff
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#define IT8368_MFIONEGINTEN_MASK 0x07ff
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#define IT8368_GPIOPOSINTSTAT_MASK 0x1fff
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#define IT8368_MFIOPOSINTSTAT_MASK 0x07ff
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#define IT8368_GPIONEGINTSTAT_MASK 0x1fff
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#define IT8368_MFIONEGINTSTAT_MASK 0x07ff
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#define IT8368_CTRL_FIXATTRIO 0x8000
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#define IT8368_FIXATTR_OFFSET 0x02000000
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#define IT8368_FIXIO_OFFSET 0x0
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#define IT8368_FIXIOATTR_SIZE 0x02000000
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#define IT8368_CTRL_ADDRSEL 0x0010
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#define IT8368_CTRL_BYTESWAP 0x0008
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#define IT8368_CTRL_CARDEN 0x0004
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#define IT8368_CTRL_GLOBALEN 0x0002
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#define IT8368_CTRL_INTTRIEN 0x0001
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#define IT8368_PIN_CRDSW 0x1000
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#define IT8368_PIN_CRDDET2 0x0800
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#define IT8368_PIN_CRDDET1 0x0400
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#define IT8368_PIN_CRDSENSE2 0x0200
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#define IT8368_PIN_CRDSENSE1 0x0100
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#define IT8368_PIN_CRDVCCON1 0x0080
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#define IT8368_PIN_CRDVCCON0 0x0040
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#define IT8368_PIN_CRDVPPON1 0x0020
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#define IT8368_PIN_CRDVPPON0 0x0010
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#define IT8368_PIN_BCRDWP 0x0008
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#define IT8368_PIN_BCRDRDY 0x0004
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#define IT8368_PIN_BCRBVD2 0x0002
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#define IT8368_PIN_BCRDRST 0x0001
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#define IT8368_PIN_CRDVCCMASK 0x00c0
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#define IT8368_PIN_CRDVPPMASK 0x0030
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#define IT8368_PIN_CRDVCC_0V 0x0000
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#define IT8368_PIN_CRDVCC_3V IT8368_PIN_CRDVCCON0
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#define IT8368_PIN_CRDVCC_5V IT8368_PIN_CRDVCCON1
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#define IT8368_PIN_CRDVPP_0V 0x0000
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#define IT8368_PIN_CRDVPP_CRDVCC IT8368_PIN_CRDVPPON0
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#define IT8368_PIN_CRDVCC_12V IT8368_PIN_CRDVPPON1
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#define IT8368_PIN_CRDVCC_HIZ (IT8368_PIN_CRDVPPON0 | \
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IT8368_PIN_CRDVPPON1)
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