245 lines
11 KiB
C
245 lines
11 KiB
C
/* $NetBSD: sh5_pcireg.h,v 1.1 2002/09/28 11:16:37 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH5_PCIREG_H
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#define _SH5_PCIREG_H
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/*
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* Offsets from the base of the PCI bridge's SuperHyWay p-port
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*/
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#define SH5PCI_MEMORY_OFFSET 0x00000000 /* PCI memory space */
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#define SH5PCI_MEMORY_SIZE 0x20000000 /* 512MB */
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#define SH5PCI_IO_OFFSET 0x20800000 /* PCI i/o space */
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#define SH5PCI_IO_SIZE 0x800000 /* 8MB */
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#define SH5PCI_VCR_OFFSET 0x20000000 /* Version Control Register */
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#define SH5PCI_CSR_OFFSET 0x20040000 /* PCIbus control registers */
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#define SH5PCI_CSR_SIZE 0x220
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/*
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* The PCI Module's "Module ID" as found in the VCR
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*/
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#define SH5PCI_MODULE_ID 0x204f
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/*
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* Offsets for the bridge's Memory and I/O BARs in PCI configuration space
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*/
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#define SH5PCI_CONF_IOBAR (PCI_MAPREG_START)
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#define SH5PCI_CONF_MBAR(n) (PCI_MAPREG_START + 0x04 + ((n) * 4))
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#define SH5PCI_NUM_MBARS 2
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/*
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* Offset for the CSR registers
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*/
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#define SH5PCI_CSR_CR 0x100 /* Control Register */
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#define SH5PCI_CSR_LSR(n) (0x104+((n)*4)) /* Local Space Register */
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#define SH5PCI_CSR_LAR(n) (0x10c+((n)*4)) /* Local Address Register */
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#define SH5PCI_CSR_INT 0x114 /* Interrupt Register */
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#define SH5PCI_CSR_INTM 0x118 /* Interrupt Msk Register */
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#define SH5PCI_CSR_AIR 0x11c /* Error Addr Info Register */
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#define SH5PCI_CSR_CIR 0x120 /* Error Comand Info Register */
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#define SH5PCI_CSR_AINT 0x130 /* Arbiter Interrupt Register */
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#define SH5PCI_CSR_AINTM 0x134 /* Arbiter Int Mask Register */
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#define SH5PCI_CSR_BMIR 0x138 /* Arbiter BM Info Register */
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#define SH5PCI_CSR_PAR 0x1c0 /* PIO Address Register */
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#define SH5PCI_CSR_MBR 0x1c4 /* Memory Space Bank Register */
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#define SH5PCI_CSR_IOBR 0x1c8 /* I/O Space Bank Register */
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#define SH5PCI_CSR_PINT 0x1cc /* Power Mgmnt Int Register */
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#define SH5PCI_CSR_PINTM 0x1d0 /* Power Mgt Int Msk Register */
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#define SH5PCI_CSR_MBMR 0x1d8 /* Mem Spc Bank Mask Register */
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#define SH5PCI_CSR_IOBMR 0x1dc /* I/O Spc Bank Mask Register */
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#define SH5PCI_CSR_CSCR0 0x210 /* Cache Snoop Ctl Register 0 */
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#define SH5PCI_CSR_CSCR1 0x214 /* Cache Snoop Ctl Register 1 */
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#define SH5PCI_CSR_CSAR0 0x218 /* Cache Snoop Adr Register 0 */
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#define SH5PCI_CSR_CSAR1 0x21c /* Cache Snoop Adr Register 1 */
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#define SH5PCI_CSR_PDR 0x220 /* PIO Data Register */
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/*
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* Bit Definitons for SH5PCI_CSR_CR PCI Control Register
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*/
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#define SH5PCI_CSR_CR_PCI_DLLDLAY_WR(v) (0xa5000000 | (((v) & 0x1ff) << 15))
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#define SH5PCI_CSR_CR_PCI_DLLDLAY(v) (((v) >> 15) & 0x1ff)
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#define SH5PCI_CSR_CR_PCI_DLLLOCK_WR(v) (0xa5000000 | (((v) & 0x1) << 14))
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#define SH5PCI_CSR_CR_PCI_DLLLOCK(v) (((v) >> 14) & 0x1)
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#define SH5PCI_CSR_CR_PCI_PBAM_WR(v) (0xa5000000 | (((v) & 0x1) << 12))
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#define SH5PCI_CSR_CR_PCI_PBAM(v) (((v) >> 12) & 0x1)
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#define SH5PCI_CSR_CR_PCI_PFCS_WR(v) (0xa5000000 | (((v) & 0x1) << 11))
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#define SH5PCI_CSR_CR_PCI_PFCS(v) (((v) >> 11) & 0x1)
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#define SH5PCI_CSR_CR_PCI_FTO_WR(v) (0xa5000000 | (((v) & 0x1) << 10))
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#define SH5PCI_CSR_CR_PCI_FTO(v) (((v) >> 10) & 0x1)
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#define SH5PCI_CSR_CR_PCI_PFE_WR(v) (0xa5000000 | (((v) & 0x1) << 9))
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#define SH5PCI_CSR_CR_PCI_PFE(v) (((v) >> 9) & 0x1)
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#define SH5PCI_CSR_CR_PCI_TBS_WR(v) (0xa5000000 | (((v) & 0x1) << 8))
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#define SH5PCI_CSR_CR_PCI_TBS(v) (((v) >> 8) & 0x1)
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#define SH5PCI_CSR_CR_PCI_SPUE_WR(v) (0xa5000000 | (((v) & 0x1) << 7))
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#define SH5PCI_CSR_CR_PCI_SPUE(v) (((v) >> 7) & 0x1)
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#define SH5PCI_CSR_CR_PCI_BMAM_WR(v) (0xa5000000 | (((v) & 0x1) << 6))
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#define SH5PCI_CSR_CR_PCI_BMAM(v) (((v) >> 6) & 0x1)
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#define SH5PCI_CSR_CR_PCI_HOSTNS(v) (((v) >> 5) & 0x1)
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#define SH5PCI_CSR_CR_PCI_CLKENS(v) (((v) >> 4) & 0x1)
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#define SH5PCI_CSR_CR_PCI_SOCS_WR(v) (0xa5000000 | (((v) & 0x1) << 3))
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#define SH5PCI_CSR_CR_PCI_SOCS(v) (((v) >> 3) & 0x1)
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#define SH5PCI_CSR_CR_PCI_IOCS_WR(v) (0xa5000000 | (((v) & 0x1) << 2))
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#define SH5PCI_CSR_CR_PCI_IOCS(v) (((v) >> 2) & 0x1)
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#define SH5PCI_CSR_CR_PCI_CFINT_WR(v) (0xa5000000 | (((v) & 0x1) << 0))
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#define SH5PCI_CSR_CR_PCI_CFINT(v) (((v) >> 0) & 0x1)
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/*
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* Bit Definitons for SH5PCI_CSR_LSR[01] PCI Local Space Register 0-1
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*/
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#define SH5PCI_CSR_LSR_PCI_LSR_WR(s) ((s) << 20)
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#define SH5PCI_CSR_LSR_PCI_LSR_SIZE(s) (((s) | 0x000fffff) + 1)
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#define SH5PCI_CSR_LSR_PCI_MBARE (1 << 0)
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#define SH5PCI_MB2LSR(mb) ((mb) - 1)
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/*
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* Bit Definitons for SH5PCI_CSR_LAR[01] PCI Local Address Register 0-1
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*/
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#define SH5PCI_CSR_LAR_PCI_LAR(s,lsr) \
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((s) & (0xc0000000 | ((~(lsr)) & 0x3ff00000)))
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/*
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* Bit Definitons for SH5PCI_CSR_INT PCI Interrupt Register
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*/
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#define SH5PCI_CSR_INT_PCI_TTADI (1 << 14) /* Master Tgt Abort */
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#define SH5PCI_CSR_INT_PCI_TMTO (1 << 9) /* Target mem rd/wr timeout */
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#define SH5PCI_CSR_INT_PCI_MDEI (1 << 8) /* Master Func. Disable Err */
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#define SH5PCI_CSR_INT_PCI_APEDI (1 << 7) /* Target Addr Parity Error */
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#define SH5PCI_CSR_INT_PCI_SDI (1 << 6) /* SERR Interrupt */
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#define SH5PCI_CSR_INT_PCI_DPEITW (1 << 5) /* Target data wr par Err */
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#define SH5PCI_CSR_INT_PCI_DEDITR (1 << 4) /* Target PERR read Err */
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#define SH5PCI_CSR_INT_PCI_TADIM (1 << 3) /* Master Target Abort */
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#define SH5PCI_CSR_INT_PCI_MADIM (1 << 2) /* Master Abort */
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#define SH5PCI_CSR_INT_PCI_MWPDI (1 << 1) /* Master PERR write Err */
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#define SH5PCI_CSR_INT_PCI_MRDPEI (1 << 0) /* Master data rd par Err */
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/*
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* Bit Definitons for SH5PCI_CSR_INTM PCI Interrupt Mask Register
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*/
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#define SH5PCI_CSR_INTM_PCI_TTADIM (1 << 14) /* Master Tgt Abort */
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#define SH5PCI_CSR_INTM_PCI_TMTOM (1 << 9) /* Target mem rd/wr timeout */
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#define SH5PCI_CSR_INTM_PCI_MDEIM (1 << 8) /* Master Func. Disable Err */
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#define SH5PCI_CSR_INTM_PCI_APEDIM (1 << 7) /* Target Addr Parity Error */
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#define SH5PCI_CSR_INTM_PCI_SDIM (1 << 6) /* SERR Interrupt */
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#define SH5PCI_CSR_INTM_PCI_DPEITWM (1 << 5) /* Target data wr par Err */
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#define SH5PCI_CSR_INTM_PCI_DEDITRM (1 << 4) /* Target PERR read Err */
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#define SH5PCI_CSR_INTM_PCI_TADIMM (1 << 3) /* Master Target Abort */
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#define SH5PCI_CSR_INTM_PCI_MADIMM (1 << 2) /* Master Abort */
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#define SH5PCI_CSR_INTM_PCI_MWPDIM (1 << 1) /* Master PERR write Err */
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#define SH5PCI_CSR_INTM_PCI_MRDPEIM (1 << 0) /* Master data rd par Err */
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/*
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* Bit Definitons for SH5PCI_CSR_CIR PCI Error Comand Info Register
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*/
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#define SH5PCI_CSR_CIR_PCI_PIOTEM (1 << 31) /* Master mem/io Xfer Error */
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#define SH5PCI_CSR_CIR_PCI_RWTET (1 << 26) /* Target rd/wr Xfer Error */
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#define SH5PCI_CSR_CIR_PCI_ECR(v) ((v)&0xf) /* Error Command Register */
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/*
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* Bit Definitons for SH5PCI_CSR_AINT PCI Arbiter Interrupt Register
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*/
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#define SH5PCI_CSR_AINT_PCI_MBI (1 << 13) /* Master Broken */
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#define SH5PCI_CSR_AINT_PCI_TBTOI (1 << 12) /* Target Bus Timeout */
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#define SH5PCI_CSR_AINT_PCI_MBTOI (1 << 11) /* Master Bus Timeout */
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#define SH5PCI_CSR_AINT_PCI_TAI (1 << 3) /* Target Abort */
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#define SH5PCI_CSR_AINT_PCI_MAI (1 << 2) /* Master Abort */
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#define SH5PCI_CSR_AINT_PCI_RDPEI (1 << 1) /* Read Data Parity Error */
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#define SH5PCI_CSR_AINT_PCI_WDPEI (1 << 0) /* Write Data Parity Error */
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/*
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* Bit Definitons for SH5PCI_CSR_AINTM PCI Arbiter Interrupt Mask Register
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*/
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#define SH5PCI_CSR_AINTM_PCI_MBIM (1 << 13) /* Master Broken */
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#define SH5PCI_CSR_AINTM_PCI_TBTOIM (1 << 12) /* Target Bus Timeout */
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#define SH5PCI_CSR_AINTM_PCI_MBTOIM (1 << 11) /* Master Bus Timeout */
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#define SH5PCI_CSR_AINTM_PCI_TAIM (1 << 3) /* Target Abort */
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#define SH5PCI_CSR_AINTM_PCI_MAIM (1 << 2) /* Master Abort */
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#define SH5PCI_CSR_AINTM_PCI_RDPEIM (1 << 1) /* Read Data Parity Error */
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#define SH5PCI_CSR_AINTM_PCI_WDPEIM (1 << 0) /* Write Data Parity Error */
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/*
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* Bit Definitons for SH5PCI_CSR_BMIR PCI Arbiter Bus Master Info Register
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*/
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#define SH5PCI_CSR_BMIR_PCI_REQBME(n) (1 << (n))
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/*
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* Bit Definitons for SH5PCI_CSR_PAR PCI PIO Address Register
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*/
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#define SH5PCI_CSR_PAR_PCI_CCIE (1 << 31)
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#define SH5PCI_CSR_PAR_PCI_BN(v) (((v) >> 16) & 0xff)
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#define SH5PCI_CSR_PAR_PCI_DN(v) (((v) >> 11) & 0x1f)
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#define SH5PCI_CSR_PAR_PCI_FN(v) (((v) >> 8) & 0x07)
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#define SH5PCI_CSR_PAR_PCI_CRA(v) ((v) & 0x0xff)
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#define SH5PCI_CSR_PAR_MAKE(b,d,f,r) \
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((((b)&0xff)<<16)|(((d)&0x1f)<<11)|(((f)&0x7)<<8)|((d)&0xfc))
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/*
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* Bit Definitons for SH5PCI_CSR_MBR PCI Memory Space Bank Register
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* and SH5PCI_CSR_IOBR PCI I/O Space Bank Register
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*/
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#define SH5PCI_CSR_BR_PCI_PSBA(a) ((a) & 0xfffc0000)
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/*
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* Bit Definitons for SH5PCI_CSR_MBMR PCI Memory Space Bank Mask Register
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*/
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#define SH5PCI_CSR_MBMR_PCI_MSBAMR(s) ((s) << 18)
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#define SH5PCI_KB2MSBAMR(kb) (((kb)==256)?0:1)
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#define SH5PCI_MB2MSBAMR(mb) ((((mb) - 1) << 2) | 0x3)
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/*
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* Bit Definitons for SH5PCI_CSR_IOBMR PCI I/O Space Bank Mask Register
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*/
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#define SH5PCI_CSR_IOBMR_PCI_IOBAMR(s) ((s) << 18)
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#define SH5PCI_KB2IOBAMR(kb) (((kb)==256)?0:1)
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#define SH5PCI_MB2IOBAMR(mb) ((((mb) - 1) << 2) | 0x3)
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/*
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* Bit Definitons for SH5PCI_CSR_CSCR[01] PCI Cache Snoop Control Registers
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*/
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#define SH5PCI_CSR_CSCR_SNPMD_DISABLED 0
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#define SH5PCI_CSR_CSCR_SNPMD_ISSUE_MISS 2
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#define SH5PCI_CSR_CSCR_SNPMD_ISSUE_HIT 3
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#define SH5PCI_CSR_CSCR_RANGE_4KB (0 << 2)
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#define SH5PCI_CSR_CSCR_RANGE_64KB (1 << 2)
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#define SH5PCI_CSR_CSCR_RANGE_1MB (2 << 2)
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#define SH5PCI_CSR_CSCR_RANGE_16MB (3 << 2)
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#define SH5PCI_CSR_CSCR_RANGE_32MB (4 << 2)
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#define SH5PCI_CSR_CSCR_RANGE_64MB (5 << 2)
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#define SH5PCI_CSR_CSCR_RANGE_128MB (6 << 2)
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#define SH5PCI_CSR_CSCR_RANGE_256MB (7 << 2)
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#endif /* _SH5_PCIREG_H */
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