115 lines
4.5 KiB
C
115 lines
4.5 KiB
C
/* $NetBSD: conreg.h,v 1.3 2002/09/12 12:35:00 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* SH-5 Control and Configuration Registers
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*/
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#ifndef _SH5_CONREG_H
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#define _SH5_CONREG_H
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/*
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* Bit definitions for Status Register (sr, ssr, pssr)
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*/
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#define SH5_CONREG_SR_S (1<<1) /* Saturation Control */
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#define SH5_CONREG_SR_IMASK_MASK 0xf /* Interrupt Mask */
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#define SH5_CONREG_SR_IMASK_SHIFT 4 /* Shift for interrupt mask */
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#define SH5_CONREG_SR_IMASK_ALL 0xf0 /* Mask all interrupts */
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#define SH5_CONREG_SR_IMASK_IPL0 0x00 /* IPLs 0 - 15 */
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#define SH5_CONREG_SR_IMASK_IPL1 0x10
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#define SH5_CONREG_SR_IMASK_IPL2 0x20
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#define SH5_CONREG_SR_IMASK_IPL3 0x30
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#define SH5_CONREG_SR_IMASK_IPL4 0x40
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#define SH5_CONREG_SR_IMASK_IPL5 0x50
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#define SH5_CONREG_SR_IMASK_IPL6 0x60
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#define SH5_CONREG_SR_IMASK_IPL7 0x70
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#define SH5_CONREG_SR_IMASK_IPL8 0x80
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#define SH5_CONREG_SR_IMASK_IPL9 0x90
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#define SH5_CONREG_SR_IMASK_IPL10 0xa0
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#define SH5_CONREG_SR_IMASK_IPL11 0xb0
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#define SH5_CONREG_SR_IMASK_IPL12 0xc0
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#define SH5_CONREG_SR_IMASK_IPL13 0xd0
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#define SH5_CONREG_SR_IMASK_IPL14 0xe0
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#define SH5_CONREG_SR_IMASK_IPL15 0xf0
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#define SH5_CONREG_SR_Q (1<<8) /* State for divide step */
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#define SH5_CONREG_SR_M (1<<9) /* Floating point precision */
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#define SH5_CONREG_SR_CD (1<<11) /* Clock tick ctr disable */
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#define SH5_CONREG_SR_PR (1<<12) /* Floating point precision */
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#define SH5_CONREG_SR_SZ (1<<13) /* Floating point tran. size */
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#define SH5_CONREG_SR_FR (1<<14) /* Floating point reg. bank */
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#define SH5_CONREG_SR_FD (1<<15) /* Floating point disable */
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#define SH5_CONREG_SR_FD_SHIFT 15
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#define SH5_CONREG_SR_ASID_MASK 0xff
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#define SH5_CONREG_SR_ASID_SHIFT 16 /* ASID Shift */
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#define SH5_CONREG_SR_WATCH (1<<26) /* Watchpoint enable flag */
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#define SH5_CONREG_SR_STEP (1<<27) /* Single-step enable flag */
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#define SH5_CONREG_SR_BL (1<<28) /* Block ALL exceptions */
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#define SH5_CONREG_SR_BL_SHIFT 28
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#define SH5_CONREG_SR_MD (1<<30) /* User/Priv Mode flag */
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#define SH5_CONREG_SR_MD_SHIFT 30
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#define SH5_CONREG_SR_MMU (1<<31) /* MMU Enable flag */
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#define SH5_CONREG_SR_MMU_SHIFT 31
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#define SH5_CONREG_SR_INIT SH5_CONREG_SR_MMU
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/*
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* Bit definitions for USR register
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*/
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#define SH5_CONREG_USR_GPRS_MASK 0xff /* GP Reg dirty state mask */
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#define SH5_CONREG_USR_GPRS_SHIFT 0 /* GP Reg dirty state shift */
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#define SH5_CONREG_USR_FPRS_MASK 0xff /* FP Reg dirty state mask */
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#define SH5_CONREG_USR_FPRS_SHIFT 8 /* FP Reg dirty state shift */
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#define SH5_GP_IS_DIRTY(usr,r) ((usr & (1 << ((r)/8))) != 0)
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#define SH5_FP_IS_DIRTY(usr,r) ((usr & (1 << (8+((r)/8)))) != 0)
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#if defined(_KERNEL) && !defined(_LOCORE)
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static __inline u_int
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sh5_getctc(void)
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{
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u_int64_t rv;
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__asm __volatile("getcon ctc, %0" : "=r"(rv));
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return ((u_int)rv);
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}
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extern u_int sh5_setasid(u_int);
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#endif
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#endif /* _SH5_CONREG_H */
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