124 lines
5.3 KiB
C
124 lines
5.3 KiB
C
/* $NetBSD: if_qnreg.h,v 1.2 1995/11/30 00:57:04 jtc Exp $ */
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/*
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* Copyright (c) 1995 Mika Kortelainen
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mika Kortelainen
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Thanks for Aspecs Oy (Finland) for the data book for the NIC used
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* in this card and also many thanks for the Resource Management Force
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* (QuickNet card manufacturer) and especially Daniel Koch for providing
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* me with the necessary 'inside' information to write the driver.
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*
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*/
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/*
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* The QuickNet card uses the Fujitsu's MB86950B NIC (Network Interface
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* Controller) chip, located at card base address + 0xff00. NIC registers
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* are accessible only at even byte addresses, so the register offsets must
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* be multiplied by two. Actually, these registers are read/written as words.
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*
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* As the card doesn't use DMA, data is input/output at FIFO register
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* (base address + 0xff20). The card has 64K buffer memory and is pretty
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* fast despite the lack of DMA.
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*
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* The FIFO register MUST be accessed as a word (16 bits).
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*
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*/
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#define QUICKNET_NIC_BASE 0xff00
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#define NIC_DLCR0 ( 0 ) /* Transmit status */
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#define NIC_DLCR1 ( 1 * 2) /* Transmit masks */
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#define NIC_DLCR2 ( 2 * 2) /* Receive status */
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#define NIC_DLCR3 ( 3 * 2) /* Receive masks */
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#define NIC_DLCR4 ( 4 * 2) /* Transmit mode */
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#define NIC_DLCR5 ( 5 * 2) /* Receive mode */
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#define NIC_DLCR6 ( 6 * 2) /* Software reset */
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#define NIC_DLCR7 ( 7 * 2) /* TDR (LSB) */
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#define NIC_DLCR8 ( 8 * 2) /* Node ID0 */
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#define NIC_DLCR9 ( 9 * 2) /* Node ID1 */
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#define NIC_DLCR10 (10 * 2) /* Node ID2 */
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#define NIC_DLCR11 (11 * 2) /* Node ID3 */
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#define NIC_DLCR12 (12 * 2) /* Node ID4 */
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#define NIC_DLCR13 (13 * 2) /* Node ID5 */
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#define NIC_DLCR15 (15 * 2) /* TDR (MSB) */
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#define NIC_BMPR0 (16 * 2) /* Buffer memory port (FIFO) */
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#define NIC_BMPR2 (18 * 2) /* Packet length */
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#define NIC_BMPR4 (20 * 2) /* DMA enable */
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#define QNET_MAGIC 0x30 /* GAL magic */
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/* DLCR0 - Transmit Status */
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#define BUS_WRITE_ERROR 0x0101 /* Bus write error */
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#define T_SIXTEEN_COL 0x0202 /* 16 collision */
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#define T_COL 0x0404 /* Collision */
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#define T_UNDERFLOW 0x0808 /* Underflow */
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#define T_TMT_OK 0x8080 /* Transmit okay */
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#define CLEAR_T_ERR 0x0f0f /* Clear transmit errors */
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/* DLCR1 - Transmit Interrupt Masks */
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#define INT_SIXTEEN_COL 0x0202 /* 16 Collision */
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#define INT_TMT_OK 0x8080 /* Transmit okay */
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#define CLEAR_T_MASK 0x0000 /* Clear transmit interrupt masks */
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/* DLCR2 - Receive Status */
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#define R_BUS_RD_ERR 0x4040 /* Bus read error */
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#define R_PKT_RDY 0x8080 /* Packet ready */
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#define CLEAR_R_ERR 0xcfcf /* Clear receive errors */
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/* DLCR3 - Receive Interrupt Masks */
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#define R_INT_OVR_FLO 0x0101 /* Receive buf overflow */
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#define R_INT_CRC_ERR 0x0202 /* CRC error */
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#define R_INT_ALG_ERR 0x0404 /* Alignment error */
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#define R_INT_SRT_PKT 0x0808 /* Short packet */
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#define R_INT_PKT_RDY 0x8080 /* Packet ready */
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#define CLEAR_R_MASK 0x0000 /* Clear receive intr masks */
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/* DLCR4 - Transmit Mode */
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#define NO_LOOPBACK 0x0202 /* Loopback control */
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/* DLCR5 - Receive Mode */
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/* Normal mode: accept physical address, multicast group addresses
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* which match the 1st three bytes and broadcast address.
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*/
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#define NORMAL_MODE 0x0101
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#define PROMISCUOUS_MODE 0x0303 /* Accept all packets */
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#define RM_BUF_EMP 0x4040 /* Buffer empty */
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/* DLCR6 - Enable Data Link Controller */
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#define DISABLE_DLC 0x8080 /* Disable data link controller */
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#define ENABLE_DLC 0x0000 /* Enable data link controller */
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/* DLCR8:DLCR13 - Node ID Registers */
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#define QNET_HARDWARE_ADDRESS NIC_DLCR8
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/* BMPR3:BMPR2 - Packet Length Registers (Write-only) */
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#define TRANSMIT_START 0x0080
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