174 lines
5.5 KiB
C
174 lines
5.5 KiB
C
/* $NetBSD: bus.h,v 1.3 1997/08/30 01:51:02 jonathan Exp $ */
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jonathan Stone for
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* the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* NetBSD machine-indepedent bus accessor macros/functions for Decstations.
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*/
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#ifndef _PMAX_BUS_H_
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#define _PMAX_BUS_H_
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#include <mips/locore.h> /* wbflush() */
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/*
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* Bus address and size types
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*/
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typedef u_long bus_addr_t;
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typedef u_long bus_size_t;
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/*
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* Access types for bus resources and addresses.
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*/
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typedef int bus_space_tag_t;
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typedef u_long bus_space_handle_t;
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/*
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* Read or write a 1, 2, or 4-byte quantity from/to a bus-space
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* address, as defined by (space-tag, handle, offset
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*/
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#define bus_space_read_1(t, h, o) \
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(*(volatile u_int8_t *)((h) + (o)))
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#define bus_space_read_2(t, h, o) \
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(*(volatile u_int16_t *)((h) + (o)))
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#define bus_space_read_4(t, h, o) \
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(*(volatile u_int32_t *)((h) + (o)))
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#define bus_space_write_1(t, h, o, v) \
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do { ((void)(*(volatile u_int8_t *)((h) + (o)) = (v))); } while (0)
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#define bus_space_write_2(t, h, o, v) \
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do { ((void)(*(volatile u_int16_t *)((h) + (o)) = (v))); } while (0)
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#define bus_space_write_4(t, h, o, v) \
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do { ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))); } while (0)
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/*
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* Read `count' 1, 2, or 4-byte quantities from bus-space
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* address, defined by (space-tag, handle, offset).
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* Copy to the specified buffer address.
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*/
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#define bus_space_read_multi_1(t, h, o, a, c) \
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do { \
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register int __i ; \
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for (__i = 0; i < (c); i++) \
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((u_char *)(a))[__i] = bus_space_read_1(t, h, o); \
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} while (0)
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#define bus_space_read_multi_2(t, h, o, a, c) \
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do { \
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register int __i ; \
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for (__i = 0; i < (c); i++) \
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((u_int16t_t *)(a))[__i] = bus_space_read_2(t, h, o); \
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} while (0)
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#define bus_space_read_multi_4(t, h, o, a, c) \
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do { \
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register int __i ; \
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for (__i = 0; i < (c); i++) \
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((u_int32_t *)(a))[__i] = bus_space_read_4(t, h, o); \
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} while (0)
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/*
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* Write `count' 1, 2, or 4-byte quantities to a bus-space
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* address, defined by (space-tag, handle, offset).
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* Copy from the specified buffer address.
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*/
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#define bus_space_write_multi_1(t, h, o, a, c) \
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do { \
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register int __i ; \
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for (__i = 0; i < (c); i++) \
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bus_space_write_1(t, h, o, ((u_char *)(a))[__i]); \
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} while (0)
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#define bus_space_write_multi_2(t, h, o, a, c) \
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do { \
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register int __i ; \
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for (__i = 0; i < (c); i++) \
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bus_space_write_2(t, h, o, ((u_int16_t *)(a))[__i]); \
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} while (0)
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#define bus_space_write_multi_4(t, h, o, a, c) \
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do { \
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register int __i ; \
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for (__i = 0; i < (c); i++) \
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bus_space_write_4(t, h, o, ((u_int32_t *)(a))[__i]); \
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} while (0)
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/*
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* Copy `count' 1, 2, or 4-byte values from one bus-space address
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* (t, h, o triple) to another.
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*/
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#define bus_space_copy_multi_1(t, h1, h2, o1, o2, c) \
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do { \
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register int __i ; \
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for (__i = 0; i < (c); i++) \
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bus_space_write_1(t, h1, o1, bus_space_read_1(t, h2, o2)); \
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} while (0)
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#define bus_space_copy_multi_2(t, h1, h2, o1, o2, c) \
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do { \
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register int __i ; \
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for (__i = 0; i < (c); i++) \
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bus_space_write_2(t, h1, o1, bus_space_read_2(t, h2, o2)); \
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while (0)
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#define bus_space_copy_multi_4(t, h1, h2, o1, o2, c) \
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do { \
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register int __i ; \
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for (__i = 0; i < (c); i++) \
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bus_space_write_4(t, h1, o1, bus_space_read_4(t, h2, o2)); \
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} while (0)
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/*
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* Bus-space barriers.
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* Since DECstation DMA is non-cache-coherent, we have to handle
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* consistency in software anyway (e.g., via bus -DMA, or by ensuring
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* that DMA buffers are referenced via uncached address space.
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* For now, simply do CPU writebuffer flushes and export the flags
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* to MI code.
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*/
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#define bus_space_barrier(t, h, o, l, f) \
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((void) wbflush();
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#define BUS_BARRIER_READ 0x01
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#define BUS_BARRIER_WRITE 0x02
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#endif /* _PMAX_BUS_H_ */
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