456 lines
11 KiB
C
456 lines
11 KiB
C
/*
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)dma.c 7.5 (Berkeley) 5/4/91
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* $Id: dma.c,v 1.2 1993/08/01 19:24:02 mycroft Exp $
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*/
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/*
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* DMA driver
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*/
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#include "param.h"
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#include "systm.h"
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#include "time.h"
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#include "kernel.h"
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#include "proc.h"
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#include "dmareg.h"
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#include "dmavar.h"
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#include "device.h"
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#include "../include/cpu.h"
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#include "../hp300/isr.h"
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extern void isrlink();
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extern void _insque();
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extern void _remque();
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extern void timeout();
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extern u_int kvtop();
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extern void PCIA();
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/*
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* The largest single request will be MAXPHYS bytes which will require
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* at most MAXPHYS/NBPG+1 chain elements to describe, i.e. if none of
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* the buffer pages are physically contiguous (MAXPHYS/NBPG) and the
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* buffer is not page aligned (+1).
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*/
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#define DMAMAXIO (MAXPHYS/NBPG+1)
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struct dma_chain {
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int dc_count;
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char *dc_addr;
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};
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struct dma_softc {
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struct dmadevice *sc_hwaddr;
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struct dmaBdevice *sc_Bhwaddr;
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char sc_type;
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char sc_flags;
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u_short sc_cmd;
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struct dma_chain *sc_cur;
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struct dma_chain *sc_last;
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struct dma_chain sc_chain[DMAMAXIO];
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} dma_softc[NDMA];
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/* types */
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#define DMA_B 0
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#define DMA_C 1
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/* flags */
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#define DMAF_PCFLUSH 0x01
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#define DMAF_VCFLUSH 0x02
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#define DMAF_NOINTR 0x04
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struct devqueue dmachan[NDMA + 1];
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int dmaintr();
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#ifdef DEBUG
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int dmadebug = 0;
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#define DDB_WORD 0x01 /* same as DMAGO_WORD */
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#define DDB_LWORD 0x02 /* same as DMAGO_LWORD */
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#define DDB_FOLLOW 0x04
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#define DDB_IO 0x08
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void dmatimeout();
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int dmatimo[NDMA];
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long dmahits[NDMA];
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long dmamisses[NDMA];
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long dmabyte[NDMA];
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long dmaword[NDMA];
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long dmalword[NDMA];
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#endif
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void
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dmainit()
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{
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register struct dmareg *dma = (struct dmareg *)DMA_BASE;
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register struct dma_softc *dc;
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register int i;
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char rev;
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/*
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* Determine the DMA type.
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* Don't know how to easily differentiate the A and B cards,
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* so we just hope nobody has an A card (A cards will work if
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* DMAINTLVL is set to 3).
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*/
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if (!badbaddr((char *)&dma->dma_id[2]))
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rev = dma->dma_id[2];
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else {
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rev = 'B';
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#if !defined(HP320)
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panic("dmainit: DMA card requires hp320 support");
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#endif
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}
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dc = &dma_softc[0];
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for (i = 0; i < NDMA; i++) {
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dc->sc_hwaddr = (i & 1) ? &dma->dma_chan1 : &dma->dma_chan0;
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dc->sc_Bhwaddr = (i & 1) ? &dma->dma_Bchan1 : &dma->dma_Bchan0;
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dc->sc_type = rev == 'B' ? DMA_B : DMA_C;
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dc++;
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dmachan[i].dq_forw = dmachan[i].dq_back = &dmachan[i];
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}
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dmachan[i].dq_forw = dmachan[i].dq_back = &dmachan[i];
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#ifdef DEBUG
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/* make sure timeout is really not needed */
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timeout(dmatimeout, 0, 30 * hz);
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#endif
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printf("dma: 98620%c with 2 channels, %d bit DMA\n",
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rev, rev == 'B' ? 16 : 32);
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}
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int
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dmareq(dq)
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register struct devqueue *dq;
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{
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register int i;
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register int chan;
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register int s = splbio();
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chan = dq->dq_ctlr;
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i = NDMA;
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while (--i >= 0) {
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if ((chan & (1 << i)) == 0)
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continue;
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if (dmachan[i].dq_forw != &dmachan[i])
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continue;
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insque(dq, &dmachan[i]);
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dq->dq_ctlr = i;
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splx(s);
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return(1);
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}
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insque(dq, dmachan[NDMA].dq_back);
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splx(s);
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return(0);
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}
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void
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dmafree(dq)
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register struct devqueue *dq;
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{
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int unit = dq->dq_ctlr;
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register struct dma_softc *dc = &dma_softc[unit];
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register struct devqueue *dn;
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register int chan, s;
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s = splbio();
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#ifdef DEBUG
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dmatimo[unit] = 0;
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#endif
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DMA_CLEAR(dc);
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/*
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* XXX we may not always go thru the flush code in dmastop()
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*/
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#if defined(HP360) || defined(HP370)
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if (dc->sc_flags & DMAF_PCFLUSH) {
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PCIA();
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dc->sc_flags &= ~DMAF_PCFLUSH;
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}
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#endif
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#if defined(HP320) || defined(HP350)
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if (dc->sc_flags & DMAF_VCFLUSH) {
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/*
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* 320/350s have VACs that may also need flushing.
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* In our case we only flush the supervisor side
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* because we know that if we are DMAing to user
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* space, the physical pages will also be mapped
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* in kernel space (via vmapbuf) and hence cache-
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* inhibited by the pmap module due to the multiple
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* mapping.
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*/
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DCIS();
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dc->sc_flags &= ~DMAF_VCFLUSH;
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}
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#endif
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remque(dq);
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chan = 1 << unit;
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for (dn = dmachan[NDMA].dq_forw;
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dn != &dmachan[NDMA]; dn = dn->dq_forw) {
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if (dn->dq_ctlr & chan) {
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remque((caddr_t)dn);
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insque((caddr_t)dn, (caddr_t)dq->dq_back);
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splx(s);
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dn->dq_ctlr = dq->dq_ctlr;
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(dn->dq_driver->d_start)(dn->dq_unit);
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return;
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}
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}
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splx(s);
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}
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void
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dmago(unit, addr, count, flags)
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int unit;
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register char *addr;
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register int count;
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register int flags;
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{
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register struct dma_softc *dc = &dma_softc[unit];
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register struct dma_chain *dcp;
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register char *dmaend = NULL;
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register int tcount;
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if (count > MAXPHYS)
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panic("dmago: count > MAXPHYS");
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#if defined(HP320)
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if (dc->sc_type == DMA_B && (flags & DMAGO_LWORD))
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panic("dmago: no can do 32-bit DMA");
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#endif
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#ifdef DEBUG
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if (dmadebug & DDB_FOLLOW)
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printf("dmago(%d, %x, %x, %x)\n",
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unit, addr, count, flags);
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if (flags & DMAGO_LWORD)
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dmalword[unit]++;
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else if (flags & DMAGO_WORD)
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dmaword[unit]++;
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else
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dmabyte[unit]++;
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#endif
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/*
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* Build the DMA chain
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*/
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for (dcp = dc->sc_chain; count > 0; dcp++) {
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dcp->dc_addr = (char *) kvtop(addr);
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if (count < (tcount = NBPG - ((int)addr & PGOFSET)))
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tcount = count;
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dcp->dc_count = tcount;
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addr += tcount;
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count -= tcount;
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if (flags & DMAGO_LWORD)
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tcount >>= 2;
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else if (flags & DMAGO_WORD)
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tcount >>= 1;
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if (dcp->dc_addr == dmaend
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#if defined(HP320)
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/* only 16-bit count on 98620B */
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&& (dc->sc_type != DMA_B ||
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(dcp-1)->dc_count + tcount <= 65536)
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#endif
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) {
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#ifdef DEBUG
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dmahits[unit]++;
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#endif
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dmaend += dcp->dc_count;
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(--dcp)->dc_count += tcount;
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} else {
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#ifdef DEBUG
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dmamisses[unit]++;
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#endif
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dmaend = dcp->dc_addr + dcp->dc_count;
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dcp->dc_count = tcount;
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}
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}
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dc->sc_cur = dc->sc_chain;
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dc->sc_last = --dcp;
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dc->sc_flags = 0;
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/*
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* Set up the command word based on flags
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*/
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dc->sc_cmd = DMA_ENAB | DMA_IPL(DMAINTLVL) | DMA_START;
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if ((flags & DMAGO_READ) == 0)
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dc->sc_cmd |= DMA_WRT;
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if (flags & DMAGO_LWORD)
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dc->sc_cmd |= DMA_LWORD;
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else if (flags & DMAGO_WORD)
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dc->sc_cmd |= DMA_WORD;
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if (flags & DMAGO_PRI)
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dc->sc_cmd |= DMA_PRI;
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#if defined(HP360) || defined(HP370)
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/*
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* Remember if we need to flush external physical cache when
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* DMA is done. We only do this if we are reading (writing memory).
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*/
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if (ectype == EC_PHYS && (flags & DMAGO_READ))
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dc->sc_flags |= DMAF_PCFLUSH;
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#endif
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#if defined(HP320) || defined(HP350)
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if (ectype == EC_VIRT && (flags & DMAGO_READ))
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dc->sc_flags |= DMAF_VCFLUSH;
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#endif
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/*
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* Remember if we can skip the dma completion interrupt on
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* the last segment in the chain.
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*/
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if (flags & DMAGO_NOINT) {
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if (dc->sc_cur == dc->sc_last)
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dc->sc_cmd &= ~DMA_ENAB;
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else
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dc->sc_flags |= DMAF_NOINTR;
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}
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#ifdef DEBUG
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if (dmadebug & DDB_IO)
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if ((dmadebug&DDB_WORD) && (dc->sc_cmd&DMA_WORD) ||
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(dmadebug&DDB_LWORD) && (dc->sc_cmd&DMA_LWORD)) {
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printf("dmago: cmd %x, flags %x\n",
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dc->sc_cmd, dc->sc_flags);
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for (dcp = dc->sc_chain; dcp <= dc->sc_last; dcp++)
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printf(" %d: %d@%x\n", dcp-dc->sc_chain,
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dcp->dc_count, dcp->dc_addr);
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}
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dmatimo[unit] = 1;
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#endif
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DMA_ARM(dc);
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}
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void
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dmastop(unit)
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register int unit;
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{
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register struct dma_softc *dc = &dma_softc[unit];
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register struct devqueue *dq;
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#ifdef DEBUG
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if (dmadebug & DDB_FOLLOW)
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printf("dmastop(%d)\n", unit);
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dmatimo[unit] = 0;
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#endif
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DMA_CLEAR(dc);
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#if defined(HP360) || defined(HP370)
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if (dc->sc_flags & DMAF_PCFLUSH) {
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PCIA();
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dc->sc_flags &= ~DMAF_PCFLUSH;
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}
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#endif
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#if defined(HP320) || defined(HP350)
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if (dc->sc_flags & DMAF_VCFLUSH) {
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/*
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* 320/350s have VACs that may also need flushing.
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* In our case we only flush the supervisor side
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* because we know that if we are DMAing to user
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* space, the physical pages will also be mapped
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* in kernel space (via vmapbuf) and hence cache-
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* inhibited by the pmap module due to the multiple
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* mapping.
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*/
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DCIS();
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dc->sc_flags &= ~DMAF_VCFLUSH;
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}
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#endif
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/*
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* We may get this interrupt after a device service routine
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* has freed the dma channel. So, ignore the intr if there's
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* nothing on the queue.
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*/
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dq = dmachan[unit].dq_forw;
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if (dq != &dmachan[unit])
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(dq->dq_driver->d_done)(dq->dq_unit);
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}
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int
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dmaintr()
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{
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register struct dma_softc *dc;
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register int i, stat;
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int found = 0;
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#ifdef DEBUG
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if (dmadebug & DDB_FOLLOW)
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printf("dmaintr\n");
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#endif
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for (i = 0, dc = dma_softc; i < NDMA; i++, dc++) {
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stat = DMA_STAT(dc);
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if ((stat & DMA_INTR) == 0)
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continue;
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found++;
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#ifdef DEBUG
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if (dmadebug & DDB_IO) {
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if ((dmadebug&DDB_WORD) && (dc->sc_cmd&DMA_WORD) ||
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(dmadebug&DDB_LWORD) && (dc->sc_cmd&DMA_LWORD))
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printf("dmaintr: unit %d stat %x next %d\n",
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i, stat, (dc->sc_cur-dc->sc_chain)+1);
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}
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if (stat & DMA_ARMED)
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printf("dma%d: intr when armed\n", i);
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#endif
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if (++dc->sc_cur <= dc->sc_last) {
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#ifdef DEBUG
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dmatimo[i] = 1;
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#endif
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/*
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* Last chain segment, disable DMA interrupt.
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*/
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if (dc->sc_cur == dc->sc_last &&
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(dc->sc_flags & DMAF_NOINTR))
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dc->sc_cmd &= ~DMA_ENAB;
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DMA_CLEAR(dc);
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DMA_ARM(dc);
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} else
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dmastop(i);
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}
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return(found);
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}
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#ifdef DEBUG
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void
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dmatimeout()
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{
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register int i, s;
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for (i = 0; i < NDMA; i++) {
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s = splbio();
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if (dmatimo[i]) {
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if (dmatimo[i] > 1)
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printf("dma%d: timeout #%d\n",
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i, dmatimo[i]-1);
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dmatimo[i]++;
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}
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splx(s);
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}
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timeout(dmatimeout, (caddr_t)0, 30 * hz);
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}
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#endif
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