346 lines
8.7 KiB
C
346 lines
8.7 KiB
C
/* $NetBSD: tx3912video.c,v 1.4 1999/12/23 16:56:16 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include "opt_tx39_debug.h"
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#include "fb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <machine/bus.h>
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#include <machine/bootinfo.h> /* bootinfo */
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#include <hpcmips/tx/tx39var.h>
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#include <hpcmips/tx/tx3912videovar.h>
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#include <hpcmips/tx/tx3912videoreg.h>
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#if NFB > 0
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#include <dev/rcons/raster.h>
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#include <dev/wscons/wsdisplayvar.h>
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#include <arch/hpcmips/dev/fbvar.h>
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#endif
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void tx3912video_framebuffer_init __P((tx_chipset_tag_t, u_int32_t,
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u_int32_t));
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int tx3912video_framebuffer_alloc __P((tx_chipset_tag_t, u_int32_t,
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int, int, int, u_int32_t*,
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u_int32_t*));
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void tx3912video_reset __P((tx_chipset_tag_t));
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void tx3912video_resolution_init __P((tx_chipset_tag_t, int, int));
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int tx3912video_fbdepth __P((tx_chipset_tag_t, int));
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static u_int32_t framebuffer, framebuffersize;
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int tx3912video_match __P((struct device*, struct cfdata*, void*));
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void tx3912video_attach __P((struct device*, struct device*, void*));
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int tx3912video_print __P((void*, const char*));
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struct tx3912video_softc {
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struct device sc_dev;
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u_int32_t sc_fbaddr;
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u_int32_t sc_fbsize;
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};
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struct fb_attach_args {
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const char *fba_name;
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};
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struct cfattach tx3912video_ca = {
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sizeof(struct tx3912video_softc), tx3912video_match,
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tx3912video_attach
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};
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int
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tx3912video_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return 1;
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}
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void
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tx3912video_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct txsim_attach_args *ta = aux;
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struct tx3912video_softc *sc = (void*)self;
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tx_chipset_tag_t tc = ta->ta_tc;
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struct fb_attach_args fba;
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txreg_t reg;
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printf("\n");
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sc->sc_fbaddr = framebuffer;
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sc->sc_fbsize = framebuffersize;
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printf("TMPR3912 video module [");
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tx3912video_fbdepth(tc, 1);
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printf("] frame buffer: 0x%08x-0x%08x", sc->sc_fbaddr,
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sc->sc_fbaddr + sc->sc_fbsize);
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if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
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printf("disabled.");
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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reg &= ~(TX3912_VIDEOCTRL1_DISPON |
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TX3912_VIDEOCTRL1_ENVID);
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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}
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printf("\n");
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/* Attach frame buffer device */
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#if NFB > 0
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if (!(bootinfo->bi_cnuse & BI_CNUSE_SERIAL)) {
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if (fb_cnattach(0, 0, 0, 0)) {
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panic("tx3912video_attach: can't init fb console");
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}
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}
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fba.fba_name = "fb";
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config_found(self, &fba, tx3912video_print);
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#endif
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}
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int
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tx3912video_print(aux, pnp)
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void *aux;
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const char *pnp;
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{
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return pnp ? QUIET : UNCONF;
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}
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int
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tx3912video_init(tc, fb_start, fb_width, fb_height, fb_addr, fb_size,
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fb_line_bytes)
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tx_chipset_tag_t tc;
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u_int32_t fb_start; /* Physical address */
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int fb_width, fb_height;
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u_int32_t *fb_addr, *fb_size;
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int *fb_line_bytes;
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{
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u_int32_t addr, size;
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int fb_depth;
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/* Inquire bit depth */
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fb_depth = tx3912video_fbdepth(tc, 0);
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/* Allocate framebuffer area */
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if (tx3912video_framebuffer_alloc(tc, fb_start, fb_width, fb_height,
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fb_depth, &addr, &size)) {
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return 1;
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}
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#if notyet
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tx3912video_resolution_init(tc, fb_width, fb_height);
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#else
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/* Use Windows CE setting. */
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#endif
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/* Set DMA transfer address to VID module */
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tx3912video_framebuffer_init(tc, addr, size);
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/* Syncronize framebuffer addr to frame signal */
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tx3912video_reset(tc);
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*fb_line_bytes = (fb_width * fb_depth) / 8;
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*fb_addr = addr; /* Phsical address */
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*fb_size = size;
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return 0;
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}
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int
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tx3912video_framebuffer_alloc(tc, start, h, v, depth, fb_addr, fb_size)
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tx_chipset_tag_t tc;
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u_int32_t start;
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int h, v, depth;
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u_int32_t *fb_addr, *fb_size;
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{
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struct extent_fixed ex_fixed[2];
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struct extent *ex;
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u_long addr, size;
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int err;
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/* Calcurate frame buffer size */
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size = (h * v * depth) / 8;
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/* Allocate V-RAM area */
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if (!(ex = extent_create("Frame buffer address", start,
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start + TX3912_FRAMEBUFFER_MAX,
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0, (caddr_t)ex_fixed, sizeof ex_fixed,
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EX_NOWAIT))) {
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return 1;
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}
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if((err = extent_alloc_subregion(ex, start, start + size, size,
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TX3912_FRAMEBUFFER_ALIGNMENT,
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TX3912_FRAMEBUFFER_BOUNDARY,
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EX_FAST|EX_NOWAIT, &addr))) {
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return 1;
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}
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framebuffer = addr;
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framebuffersize = size;
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*fb_addr = addr;
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*fb_size = size;
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return 0;
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}
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void
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tx3912video_framebuffer_init(tc, fb_addr, fb_size)
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tx_chipset_tag_t tc;
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u_int32_t fb_addr, fb_size;
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{
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u_int32_t reg, vaddr, bank, base;
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/* XXX currently I don't set DFVAL, so force DF signal toggled on
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* XXX each frame. */
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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reg &= ~TX3912_VIDEOCTRL1_DFMODE;
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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/* Set DMA transfer start and end address */
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bank = TX3912_VIDEOCTRL3_VIDBANK(fb_addr);
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base = TX3912_VIDEOCTRL3_VIDBASEHI(fb_addr);
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reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank);
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/* Upper address counter */
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reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base);
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tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg);
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/* Lower address counter */
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base = TX3912_VIDEOCTRL4_VIDBASELO(fb_addr + fb_size);
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reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base);
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/* Set DF-signal rate */
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reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/
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/* Set VIDDONE signal delay after FRAME signal */
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/* XXX not yet*/
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tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg);
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/* Clear frame buffer */
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vaddr = MIPS_PHYS_TO_KSEG1(fb_addr);
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bzero((void*)vaddr, fb_size);
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}
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void
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tx3912video_resolution_init(tc, h, v)
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tx_chipset_tag_t tc;
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int h;
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int v;
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{
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u_int32_t reg, val;
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int split, bit8, horzval, lineval;
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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split = reg & TX3912_VIDEOCTRL1_DISPSPLIT;
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bit8 = (TX3912_VIDEOCTRL1_BITSEL(reg) ==
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TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR);
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val = TX3912_VIDEOCTRL1_BITSEL(reg);
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if ((val == TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR) &&
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!split) {
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/* (LCD horizontal pixels / 8bit) * RGB - 1 */
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horzval = (h / 8) * 3 - 1;
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} else {
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horzval = h / 4 - 1;
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}
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lineval = (split ? v / 2 : v) - 1;
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/* Video rate */
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/* XXX
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* probably This value should be determined from DFINT and LCDINT
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*/
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reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1);
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/* Horizontal size of LCD */
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reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval);
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/* # of lines for the LCD */
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reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval);
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tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg);
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}
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int
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tx3912video_fbdepth(tc, verbose)
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tx_chipset_tag_t tc;
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int verbose;
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{
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u_int32_t reg, val;
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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val = TX3912_VIDEOCTRL1_BITSEL(reg);
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switch (val) {
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case TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR:
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if (verbose)
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printf("8bit color");
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return 8;
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case TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE:
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if (verbose)
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printf("4bit greyscale");
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return 4;
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case TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE:
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if (verbose)
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printf("2bit greyscale");
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return 2;
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case TX3912_VIDEOCTRL1_BITSEL_MONOCHROME:
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if (verbose)
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printf("monochrome");
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return 1;
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}
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return 0;
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}
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void
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tx3912video_reset(tc)
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tx_chipset_tag_t tc;
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{
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u_int32_t reg;
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reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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/* Disable video logic at end of this frame */
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reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME;
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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/* Wait for end of frame */
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delay(300 * 1000);
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/* Make sure to disable video logic */
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reg &= ~TX3912_VIDEOCTRL1_ENVID;
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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delay(1000);
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/* Enable video logic again */
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reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME;
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reg |= TX3912_VIDEOCTRL1_ENVID;
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tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
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delay(1000);
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}
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