418 lines
9.8 KiB
C
418 lines
9.8 KiB
C
/* $NetBSD: pbcpcibus.c,v 1.2 2000/01/23 21:01:59 soda Exp $ */
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/* $OpenBSD: pbcpcibus.c,v 1.4 1997/04/19 17:20:02 pefo Exp $ */
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/*
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* Copyright (c) 1997 Per Fogelstrom
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed under OpenBSD by
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* Per Fogelstrom.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* ARC PCI BUS Bridge driver.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/proc.h>
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#include <vm/vm.h>
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <arc/arc/arctype.h>
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#include <arc/algor/algor.h>
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#include <arc/pci/pcibrvar.h>
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#include <arc/pci/v962pcbreg.h>
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extern vm_map_t phys_map;
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extern int cputype;
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extern char eth_hw_addr[]; /* Hardware ethernet address stored elsewhere */
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int pbcpcibrmatch __P((struct device *, struct cfdata *, void *));
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void pbcpcibrattach __P((struct device *, struct device *, void *));
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void pbc_attach_hook __P((struct device *, struct device *,
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struct pcibus_attach_args *));
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int pbc_bus_maxdevs __P((void *, int));
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pcitag_t pbc_make_tag __P((void *, int, int, int));
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void pbc_decompose_tag __P((void *, pcitag_t, int *, int *, int *));
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pcireg_t pbc_conf_read __P((void *, pcitag_t, int));
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void pbc_conf_write __P((void *, pcitag_t, int, pcireg_t));
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int pbc_intr_map __P((void *, pcitag_t, int, int, pci_intr_handle_t *));
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const char *pbc_intr_string __P((void *, pci_intr_handle_t));
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void *pbc_intr_establish __P((void *, pci_intr_handle_t,
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int, int (*func)(void *), void *, char *));
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void pbc_intr_disestablish __P((void *, void *));
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int pbc_ether_hw_addr __P((u_int8_t *));
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struct cfattach pbcpcibr_ca = {
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sizeof(struct pcibr_softc), pbcpcibrmatch, pbcpcibrattach,
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};
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struct cfdriver pbcpcibr_cd = {
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NULL, "pbcpcibr", DV_DULL,
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};
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static int pbcpcibrprint __P((void *, const char *pnp));
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struct pcibr_config pbc_config;
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int
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pbcpcibrmatch(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct confargs *ca = aux;
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/* Make sure that we're looking for a PCI bridge. */
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if (strcmp(ca->ca_name, pbcpcibr_cd.cd_name) != 0)
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return (0);
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return (1);
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}
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void
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pbcpcibrattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct pcibr_softc *sc = (struct pcibr_softc *)self;
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struct pcibr_config *lcp;
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struct pcibus_attach_args pba;
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switch(cputype) {
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case ALGOR_P4032:
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V96X_PCI_BASE0 = V96X_PCI_BASE0 & 0xffff0000;
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lcp = sc->sc_pcibr = &pbc_config;
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sc->sc_bus_space.bus_base = V96X_PCI_MEM_SPACE;
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sc->sc_bus_space.bus_sparse1 = 0;
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sc->sc_bus_space.bus_sparse2 = 0;
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sc->sc_bus_space.bus_sparse4 = 0;
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sc->sc_bus_space.bus_sparse8 = 0;
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lcp->lc_pc.pc_conf_v = lcp;
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lcp->lc_pc.pc_attach_hook = pbc_attach_hook;
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lcp->lc_pc.pc_bus_maxdevs = pbc_bus_maxdevs;
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lcp->lc_pc.pc_make_tag = pbc_make_tag;
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lcp->lc_pc.pc_decompose_tag = pbc_decompose_tag;
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lcp->lc_pc.pc_conf_read = pbc_conf_read;
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lcp->lc_pc.pc_conf_write = pbc_conf_write;
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lcp->lc_pc.pc_ether_hw_addr = pbc_ether_hw_addr;
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lcp->lc_pc.pc_intr_v = lcp;
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lcp->lc_pc.pc_intr_map = pbc_intr_map;
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lcp->lc_pc.pc_intr_string = pbc_intr_string;
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lcp->lc_pc.pc_intr_establish = pbc_intr_establish;
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lcp->lc_pc.pc_intr_disestablish = pbc_intr_disestablish;
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printf(": V3 V962, Revision %x.\n", V96X_PCI_CC_REV);
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break;
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}
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pba.pba_busname = "pci";
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pba.pba_iot = &sc->sc_bus_space;
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pba.pba_memt = &sc->sc_bus_space;
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pba.pba_pc = &lcp->lc_pc;
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pba.pba_bus = 0;
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config_found(self, &pba, pbcpcibrprint);
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}
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static int
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pbcpcibrprint(aux, pnp)
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void *aux;
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const char *pnp;
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{
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struct pcibus_attach_args *pba = aux;
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if(pnp)
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printf("%s at %s", pba->pba_busname, pnp);
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printf(" bus %d", pba->pba_bus);
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return(UNCONF);
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}
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/*
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* Get PCI physical address from given viritual address.
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*/
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vm_offset_t
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vtophys(p)
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void *p;
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{
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vm_offset_t pa;
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vm_offset_t va;
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va = (vm_offset_t)p;
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if(va >= UADDR) { /* Stupid driver have buf on stack!! */
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va = (vm_offset_t)curproc->p_addr + (va & ~UADDR);
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}
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if((vm_offset_t)va < VM_MIN_KERNEL_ADDRESS) {
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pa = MIPS_CACHED_TO_PHYS(va);
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}
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else {
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pa = pmap_extract(vm_map_pmap(phys_map), va);
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}
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return(pa);
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}
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void
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pbc_attach_hook(parent, self, pba)
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struct device *parent, *self;
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struct pcibus_attach_args *pba;
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{
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}
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int
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pbc_bus_maxdevs(cpv, busno)
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void *cpv;
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int busno;
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{
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return(16);
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}
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pcitag_t
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pbc_make_tag(cpv, bus, dev, fnc)
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void *cpv;
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int bus, dev, fnc;
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{
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return (bus << 16) | (dev << 11) | (fnc << 8);
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}
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void
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pbc_decompose_tag(cpv, tag, busp, devp, fncp)
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void *cpv;
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pcitag_t tag;
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int *busp, *devp, *fncp;
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{
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if (busp != NULL)
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*busp = (tag >> 16) & 0xff;
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if (devp != NULL)
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*devp = (tag >> 11) & 0x1f;
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if (fncp != NULL)
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*fncp = (tag >> 8) & 0x7;
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}
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pcireg_t
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pbc_conf_read(cpv, tag, offset)
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void *cpv;
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pcitag_t tag;
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int offset;
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{
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pcireg_t data;
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u_int32_t addr;
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int device;
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int s;
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if((tag >> 16) != 0)
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return(~0);
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if(offset & 3 || offset < 0 || offset >= 0x100) {
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printf ("pci_conf_read: bad reg %x\n", offset);
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return(~0);
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}
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device = (tag >> 11) & 0x1f;
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addr = (0x800 << device) | (tag & 0x380) | offset;
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s = splhigh();
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/* clear aborts */
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V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
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/* high 12 bits of address go in map register, and set for conf space */
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V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | V96X_LB_TYPE_CONF;
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wbflush();
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/* low 20 bits of address are in the actual address */
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data = *(volatile pcireg_t *) (V96X_PCI_CONF_SPACE + (addr&0xfffff));
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if (V96X_PCI_STAT & V96X_PCI_STAT_M_ABORT) {
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V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT;
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printf ("device %d: master abort\n", device);
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return(~0);
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}
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if (V96X_PCI_STAT & V96X_PCI_STAT_T_ABORT) {
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V96X_PCI_STAT |= V96X_PCI_STAT_T_ABORT;
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printf ("PCI slot %d: target abort!\n", device);
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return(~0);
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}
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splx(s);
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return(data);
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}
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void
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pbc_conf_write(cpv, tag, offset, data)
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void *cpv;
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pcitag_t tag;
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int offset;
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pcireg_t data;
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{
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u_int32_t addr;
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int device;
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int s;
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device = (tag >> 11) & 0x1f;
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addr = (0x800 << device) | (tag & 0x380) | offset;
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s = splhigh();
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/* clear aborts */
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V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT | V96X_PCI_STAT_T_ABORT;
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/* high 12 bits of address go in map register, and set for conf space */
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V96X_LB_MAP0 = ((addr >> 16) & V96X_LB_MAPx_MAP_ADR) | V96X_LB_TYPE_CONF;
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wbflush();
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/* low 20 bits of address are in the actual address */
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*(volatile pcireg_t *) (V96X_PCI_CONF_SPACE + (addr&0xfffff)) = data;
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/* wait for write FIFO to empty */
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do {
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} while (V96X_FIFO_STAT & V96X_FIFO_STAT_L2P_WR);
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if (V96X_PCI_STAT & V96X_PCI_STAT_M_ABORT) {
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V96X_PCI_STAT |= V96X_PCI_STAT_M_ABORT;
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printf ("PCI slot %d: conf_write: master abort\n", device);
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}
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if (V96X_PCI_STAT & V96X_PCI_STAT_T_ABORT) {
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V96X_PCI_STAT |= V96X_PCI_STAT_T_ABORT;
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printf ("PCI slot %d: conf_write: target abort!\n", device);
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}
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splx(s);
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}
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/*
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* Hook to get ethernet hardware address when not in dev rom
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*/
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int
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pbc_ether_hw_addr(cp)
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u_int8_t *cp;
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{
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if(cputype == ALGOR_P4032) {
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bcopy(eth_hw_addr, cp, 6);
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return(0);
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}
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return(-1);
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}
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int
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pbc_intr_map(lcv, bustag, buspin, line, ihp)
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void *lcv;
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pcitag_t bustag;
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int buspin, line;
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pci_intr_handle_t *ihp;
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{
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struct pcibr_config *lcp = lcv;
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pci_chipset_tag_t pc = &lcp->lc_pc;
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int device, pirq;
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if (buspin == 0) {
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/* No IRQ used. */
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*ihp = -1;
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return 1;
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}
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if (buspin > 4) {
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printf("pbc_intr_map: bad interrupt pin %d\n", buspin);
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*ihp = -1;
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return 1;
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}
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pci_decompose_tag(pc, bustag, NULL, &device, NULL);
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pirq = buspin - 1;
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switch(device) {
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case 5: /* DC21041 */
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pirq = 1;
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break;
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case 8: /* NCR SCSI */
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pirq = 0;
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break;
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default:
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switch (buspin) {
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case PCI_INTERRUPT_PIN_A:
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pirq = 0;
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break;
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case PCI_INTERRUPT_PIN_B:
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pirq = 1;
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break;
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case PCI_INTERRUPT_PIN_C:
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pirq = 2;
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break;
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case PCI_INTERRUPT_PIN_D:
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pirq = 3;
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break;
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}
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}
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*ihp = pirq;
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return 0;
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}
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const char *
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pbc_intr_string(lcv, ih)
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void *lcv;
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pci_intr_handle_t ih;
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{
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static char str[16];
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sprintf(str, "pciirq%d", ih);
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return(str);
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}
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void *
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pbc_intr_establish(lcv, ih, level, func, arg, name)
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void *lcv;
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pci_intr_handle_t ih;
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int level;
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int (*func) __P((void *));
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void *arg;
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char *name;
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{
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return algor_pci_intr_establish(ih, level, func, arg, name);
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}
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void
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pbc_intr_disestablish(lcv, cookie)
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void *lcv, *cookie;
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{
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algor_pci_intr_disestablish(cookie);
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}
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