205 lines
7.3 KiB
C
205 lines
7.3 KiB
C
/* $NetBSD: cpu.h,v 1.4 1997/04/09 19:21:06 thorpej Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah $Hdr: cpu.h 1.16 91/03/25$
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*
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* @(#)cpu.h 8.4 (Berkeley) 1/5/94
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*/
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#ifndef _M68K_CPU_H_
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#define _M68K_CPU_H_
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/*
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* Exported definitions common to Motorola m68k-based ports.
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*
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* Note that are some port-specific definitions here, such as
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* HP and Sun MMU types. These facilitate adding very small
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* amounts of port-specific code to what would otherwise be
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* identical. The is especially true in the case of the HP
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* and other m68k pmaps.
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*
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* Individual ports are expected to define the following CPP symbols
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* in <machine/cpu.h> to enable conditional code:
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*
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* M68K_MMU_MOTOROLA Machine has a Motorola MMU (incl.
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* 68851, 68030, 68040, 68060)
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*
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* M68K_MMU_HP Machine has an HP MMU.
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*
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* Note also that while m68k-generic code conditionalizes on the
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* M68K_MMU_HP CPP symbol, none of the HP MMU defintions are in this
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* file (since none are used in otherwise sharable code).
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*/
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/*
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* XXX Much more could be pulled out of port-specific header files
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* XXX and placed here.
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*/
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#ifdef _KERNEL
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/*
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* All m68k ports must provide these globals.
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*/
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extern int cputype; /* CPU on this host */
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extern int ectype; /* external cache on this host */
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extern int fputype; /* FPU on this host */
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extern int mmutype; /* MMU on this host */
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#endif
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/* values for cputype */
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#define CPU_68020 0 /* 68020 */
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#define CPU_68030 1 /* 68030 */
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#define CPU_68040 2 /* 68040 */
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#define CPU_68060 3 /* 68060 */
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/* values for ectype */
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#define EC_PHYS -1 /* external physical address cache */
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#define EC_NONE 0 /* no external cache */
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#define EC_VIRT 1 /* external virtual address cache */
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/* values for fputype */
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#define FPU_NONE 0 /* no FPU */
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#define FPU_68881 1 /* 68881 FPU */
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#define FPU_68882 2 /* 68882 FPU */
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#define FPU_68040 3 /* 68040 on-chip FPU */
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#define FPU_68060 4 /* 68060 on-chip FPU */
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#define FPU_UNKNOWN 5 /* placeholder; unknown FPU */
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/* values for mmutype (assigned for quick testing) */
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#define MMU_68060 -3 /* 68060 on-chip MMU */
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#define MMU_68040 -2 /* 68040 on-chip MMU */
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#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
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#define MMU_HP 0 /* HP proprietary */
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#define MMU_68851 1 /* Motorola 68851 */
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#define MMU_SUN 2 /* Sun MMU */
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/*
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* 68851 and 68030 MMU
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*/
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#define PMMU_LVLMASK 0x0007
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#define PMMU_INV 0x0400
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#define PMMU_WP 0x0800
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#define PMMU_ALV 0x1000
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#define PMMU_SO 0x2000
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#define PMMU_LV 0x4000
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#define PMMU_BE 0x8000
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#define PMMU_FAULT (PMMU_WP|PMMU_INV)
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/*
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* 68040 MMU
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*/
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#define MMU40_RES 0x001
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#define MMU40_TTR 0x002
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#define MMU40_WP 0x004
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#define MMU40_MOD 0x010
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#define MMU40_CMMASK 0x060
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#define MMU40_SUP 0x080
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#define MMU40_U0 0x100
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#define MMU40_U1 0x200
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#define MMU40_GLB 0x400
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#define MMU40_BE 0x800
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/* 680X0 function codes */
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#define FC_USERD 1 /* user data space */
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#define FC_USERP 2 /* user program space */
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#define FC_PURGE 3 /* HPMMU: clear TLB entries */
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#define FC_SUPERD 5 /* supervisor data space */
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#define FC_SUPERP 6 /* supervisor program space */
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#define FC_CPU 7 /* CPU space */
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/* fields in the 68020 cache control register */
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#define IC_ENABLE 0x0001 /* enable instruction cache */
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#define IC_FREEZE 0x0002 /* freeze instruction cache */
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#define IC_CE 0x0004 /* clear instruction cache entry */
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#define IC_CLR 0x0008 /* clear entire instruction cache */
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/* additional fields in the 68030 cache control register */
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#define IC_BE 0x0010 /* instruction burst enable */
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#define DC_ENABLE 0x0100 /* data cache enable */
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#define DC_FREEZE 0x0200 /* data cache freeze */
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#define DC_CE 0x0400 /* clear data cache entry */
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#define DC_CLR 0x0800 /* clear entire data cache */
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#define DC_BE 0x1000 /* data burst enable */
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#define DC_WA 0x2000 /* write allocate */
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/* fields in the 68040 cache control register */
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#define IC40_ENABLE 0x00008000 /* instruction cache enable bit */
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#define DC40_ENABLE 0x80000000 /* data cache enable bit */
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/* additional fields in the 68060 cache control register */
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#define DC60_NAD 0x40000000 /* no allocate mode, data cache */
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#define DC60_ESB 0x20000000 /* enable store buffer */
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#define DC60_DPI 0x10000000 /* disable CPUSH invalidation */
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#define DC60_FOC 0x08000000 /* four kB data cache mode (else 8) */
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#define IC60_EBC 0x00800000 /* enable branch cache */
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#define IC60_CABC 0x00400000 /* clear all branch cache entries */
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#define IC60_CUBC 0x00200000 /* clear user branch cache entries */
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#define IC60_NAI 0x00004000 /* no allocate mode, instr. cache */
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#define IC60_FIC 0x00002000 /* four kB instr. cache (else 8) */
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#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define CACHE_OFF (DC_CLR|IC_CLR)
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#define CACHE_CLR (CACHE_ON)
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#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
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#define CACHE40_ON (IC40_ENABLE|DC40_ENABLE)
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#define CACHE40_OFF (0x00000000)
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#define CACHE60_ON (CACHE40_ON|IC60_CABC|IC60_EBC|DC60_ESB)
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#define CACHE60_OFF (CACHE40_OFF|IC60_CABC)
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#ifdef _KERNEL
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void copypage __P((void *fromaddr, void *toaddr));
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void zeropage __P((void *addr));
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#ifdef MAPPEDCOPY
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int mappedcopyin __P((void *fromp, void *top, size_t count));
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int mappedcopyout __P((void *fromp, void *top, size_t count));
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extern u_int mappedcopysize;
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#endif /* MAPPEDCOPY */
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struct trapframe;
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void regdump __P((struct trapframe *, int));
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#endif /* _KERNEL */
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#endif /* _M68K_CPU_H_ */
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