thorpej a5b316c4d5 Key off NSIO and NPCEB for (E)ISA interrupt support. ...

XXX Can probably nuke the SIO test; don't all of the Noritake-class systems
XXX have EISA?

1999-12-15 22:31:04 +00:00

..

a12c_bus_mem.c

…

a12c_dma.c

…

a12c_pci.c

…

a12c.c

Allow rd/line, rd/mult, and wr/inval.

1999-11-04 19:15:22 +00:00

a12creg.h

…

a12cvar.h

…

apecs_bus_io.c

…

apecs_bus_mem.c

…

apecs_dma.c

…

apecs_pci.c

…

apecs.c

Allow rd/line, rd/mult, and wr/inval.

1999-11-04 19:15:22 +00:00

apecsreg.h

…

apecsvar.h

…

cia_bwx_bus_io.c

CIA core logic with BWX enabled appears on both EV56 and PCA56. We

1999-12-02 19:43:25 +00:00

cia_bwx_bus_mem.c

CIA core logic with BWX enabled appears on both EV56 and PCA56. We

1999-12-02 19:43:25 +00:00

cia_dma.c

…

cia_pci.c

…

cia_swiz_bus_io.c

…

cia_swiz_bus_mem.c

…

cia.c

…

ciareg.h

…

ciavar.h

…

dwlpx_bus_io.c

…

dwlpx_bus_mem.c

…

dwlpx_dma.c

…

dwlpx_pci.c

…

dwlpx.c

Allow rd/line, rd/mult, and wr/inval.

1999-11-04 19:15:22 +00:00

dwlpxreg.h

…

dwlpxvar.h

…

lca_bus_io.c

…

lca_bus_mem.c

…

lca_dma.c

…

lca_pci.c

…

lca.c

Allow rd/line, rd/mult, and wr/inval.

1999-11-04 19:15:22 +00:00

lcareg.h

…

lcavar.h

…

mcpcia_bus_io.c

…

mcpcia_bus_mem.c

…

mcpcia_dma.c

…

mcpcia_pci.c

…

mcpcia.c

Make sure a MCPCIA exists before trying to initialize it. Also make

1999-11-16 18:33:11 +00:00

mcpciareg.h

…

mcpciavar.h

…

pci_550.c

…

pci_550.h

…

pci_1000.c

Key off NSIO and NPCEB for (E)ISA interrupt support.

1999-12-15 22:30:40 +00:00

pci_1000.h

…

pci_1000a.c

Key off NSIO and NPCEB for (E)ISA interrupt support.

1999-12-15 22:31:04 +00:00

pci_1000a.h

…

pci_2100_a50.c

…

pci_2100_a50.h

…

pci_6600.c

…

pci_6600.h

…

pci_a12.c

…

pci_a12.h

…

pci_alphabook1.c

…

pci_alphabook1.h

…

pci_axppci_33.c

…

pci_axppci_33.h

…

pci_bwx_bus_io_chipdep.c

Pull in the BWX inlines. We expect the arch to be set appropriately for

1999-12-02 19:44:49 +00:00

pci_bwx_bus_mem_chipdep.c

Pull in the BWX inlines. We expect the arch to be set appropriately for

1999-12-02 19:44:49 +00:00

pci_eb64plus_intr.s

…

pci_eb64plus.c

…

pci_eb64plus.h

…

pci_eb66_intr.s

…

pci_eb66.c

…

pci_eb66.h

…

pci_eb164_intr.s

…

pci_eb164.c

…

pci_eb164.h

…

pci_kn8ae.c

…

pci_kn8ae.h

…

pci_kn20aa.c

Key off NSIO and NPCEB for (E)ISA interrupt support.

1999-12-15 22:28:15 +00:00

pci_kn20aa.h

…

pci_kn300.c

Key off NSIO and NPCEB for (E)ISA interrupt support.

1999-12-15 22:25:21 +00:00

pci_kn300.h

…

pci_machdep.c

…

pci_sgmap_pte32.c

…

pci_sgmap_pte32.h

…

pci_sgmap_pte64.c

…

pci_sgmap_pte64.h

…

pci_swiz_bus_io_chipdep.c

Clarify what appear to the untrained eye to be two magic constants (the

1999-12-07 05:44:57 +00:00

pci_swiz_bus_mem_chipdep.c

Handle the case where PCI dense memory and PCI sparse memory don't

1999-12-08 01:48:39 +00:00

pciide_machdep.c

…

sio_pic.c

…

sio.c

recognise the ACER labs M1543 PCI-ISA Bridge in siomatch(). the DS10 now boots!

1999-11-12 22:07:28 +00:00

sioreg.h

…

siovar.h

…

tsc.c

Allow rd/line, rd/mult, and wr/inval.

1999-11-04 19:15:22 +00:00

tsp_bus_io.c

CIA core logic with BWX enabled appears on EV6. We require at least

1999-12-02 19:43:58 +00:00

tsp_bus_mem.c

CIA core logic with BWX enabled appears on EV6. We require at least

1999-12-02 19:43:58 +00:00

tsp_dma.c

…

tsp_pci.c

…

tsreg.h

…

tsvar.h

…