295 lines
12 KiB
C
295 lines
12 KiB
C
/* $NetBSD: dwc_gmac_reg.h,v 1.20 2020/05/17 21:50:47 chs Exp $ */
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/*-
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* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry and Martin Husemann.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define AWIN_GMAC_MAC_CONF 0x0000
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#define AWIN_GMAC_MAC_FFILT 0x0004
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#define AWIN_GMAC_MAC_HTHIGH 0x0008
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#define AWIN_GMAC_MAC_HTLOW 0x000c
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#define AWIN_GMAC_MAC_MIIADDR 0x0010
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#define AWIN_GMAC_MAC_MIIDATA 0x0014
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#define AWIN_GMAC_MAC_FLOWCTRL 0x0018
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#define AWIN_GMAC_MAC_VLANTAG 0x001c
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#define AWIN_GMAC_MAC_VERSION 0x0020 /* not always implemented? */
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#define AWIN_GMAC_MAC_INTR 0x0038
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#define AWIN_GMAC_MAC_INTMASK 0x003c
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#define AWIN_GMAC_MAC_ADDR0HI 0x0040
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#define AWIN_GMAC_MAC_ADDR0LO 0x0044
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#define AWIN_GMAC_MII_STATUS 0x00D8
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#define AWIN_GMAC_MAC_CONF_DISABLEJABBER __BIT(22) /* jabber disable */
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#define AWIN_GMAC_MAC_CONF_FRAMEBURST __BIT(21) /* allow TX frameburst when
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in half duplex mode */
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#define AWIN_GMAC_MAC_CONF_MIISEL __BIT(15) /* select MII phy */
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#define AWIN_GMAC_MAC_CONF_FES100 __BIT(14) /* 100 mbit mode */
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#define AWIN_GMAC_MAC_CONF_DISABLERXOWN __BIT(13) /* do not receive our own
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TX frames in half duplex
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mode */
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#define AWIN_GMAC_MAC_CONF_FULLDPLX __BIT(11) /* select full duplex */
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#define AWIN_GMAC_MAC_CONF_ACS __BIT(7) /* auto pad/CRC stripping */
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#define AWIN_GMAC_MAC_CONF_TXENABLE __BIT(3) /* enable TX dma engine */
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#define AWIN_GMAC_MAC_CONF_RXENABLE __BIT(2) /* enable RX dma engine */
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#define AWIN_GMAC_MAC_FFILT_RA __BIT(31) /* receive all mode */
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#define AWIN_GMAC_MAC_FFILT_HPF __BIT(10) /* hash or perfect filter */
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#define AWIN_GMAC_MAC_FFILT_SAF __BIT(9) /* source address filter */
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#define AWIN_GMAC_MAC_FFILT_SAIF __BIT(8) /* inverse filtering */
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#define AWIN_GMAC_MAC_FFILT_DBF __BIT(5) /* disable broadcast frames */
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#define AWIN_GMAC_MAC_FFILT_PM __BIT(4) /* promiscious multicast */
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#define AWIN_GMAC_MAC_FFILT_DAIF __BIT(3) /* DA inverse filtering */
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#define AWIN_GMAC_MAC_FFILT_HMC __BIT(2) /* multicast hash compare */
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#define AWIN_GMAC_MAC_FFILT_HUC __BIT(1) /* unicast hash compare */
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#define AWIN_GMAC_MAC_FFILT_PR __BIT(0) /* promiscious mode */
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#define AWIN_GMAC_MAC_INT_LPI __BIT(10)
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#define AWIN_GMAC_MAC_INT_TSI __BIT(9)
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#define AWIN_GMAC_MAC_INT_ANEG __BIT(2)
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#define AWIN_GMAC_MAC_INT_LINKCHG __BIT(1)
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#define AWIN_GMAC_MAC_INT_RGSMII __BIT(0)
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#define AWIN_GMAC_MAC_FLOWCTRL_PAUSE __BITS(31,16)
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#define AWIN_GMAC_MAC_FLOWCTRL_RFE __BIT(2)
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#define AWIN_GMAC_MAC_FLOWCTRL_TFE __BIT(1)
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#define AWIN_GMAC_MAC_FLOWCTRL_BUSY __BIT(0)
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#define GMAC_MMC_CTRL 0x0100 /* MMC control */
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#define GMAC_MMC_RX_INTR 0x0104 /* MMC RX interrupt */
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#define GMAC_MMC_TX_INTR 0x0108 /* MMC TX interrupt */
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#define GMAC_MMC_RX_INT_MSK 0x010c /* MMC RX interrupt mask */
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#define GMAC_MMC_TX_INT_MSK 0x0110 /* MMC TX interrupt mask */
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#define GMAC_MMC_TXOCTETCNT_GB 0x0114 /* TX octet good+bad */
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#define GMAC_MMC_TXFRMCNT_GB 0x0118 /* TX frame good+bad */
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#define GMAC_MMC_TXUNDFLWERR 0x0148 /* TX underflow */
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#define GMAC_MMC_TXCARERR 0x0160 /* TX carrier error */
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#define GMAC_MMC_TXOCTETCNT_G 0x0164 /* TX octet good */
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#define GMAC_MMC_TXFRMCNT_G 0x0168 /* TX frame good */
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#define GMAC_MMC_RXFRMCNT_GB 0x0180 /* RX frame good+bad */
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#define GMAC_MMC_RXOCTETCNT_GB 0x0184 /* RX octet good+bad */
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#define GMAC_MMC_RXOCTETCNT_G 0x0188 /* RX octet good */
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#define GMAC_MMC_RXMCFRMCNT_G 0x0190 /* RX mcast frame good */
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#define GMAC_MMC_RXCRCERR 0x0194 /* RX CRC error */
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#define GMAC_MMC_RXLENERR 0x01c8 /* RX length error */
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#define GMAC_MMC_RXFIFOOVRFLW 0x01d4 /* RX FIFO overflow */
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#define GMAC_MMC_IPC_INT_MSK 0x0200 /* RX csum offload intr mask */
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#define GMAC_MMC_IPC_INTR 0x0208 /* RX csum offload interrupt */
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#define GMAC_MMC_RXIPV4GFRM 0x0210 /* RX IPv4 good frame */
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#define GMAC_MMC_RXIPV4HDERRFRM 0x0214 /* RX IPv4 header error */
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#define GMAC_MMC_RXIPV6GFRM 0x0224 /* RX IPv6 good frame */
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#define GMAC_MMC_RXIPV6HDERRFRM 0x0228 /* RX IPv6 header error */
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#define GMAC_MMC_RXUDPERRFRM 0x0234 /* RX UDP csum error frame */
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#define GMAC_MMC_RXTCPERRFRM 0x023c /* RX TCP csum error frame */
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#define GMAC_MMC_RXICMPERRFRM 0x0244 /* RX ICMP csum error frame */
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#define GMAC_MMC_RXIPV4HDERROCT 0x0254 /* RX IPv4 header error octets */
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#define GMAC_MMC_RXIPV6HDERROCT 0x0268 /* RX IPv6 header error octets */
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#define GMAC_MMC_RXUDPERROCT 0x0274 /* RX UDP error octets */
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#define GMAC_MMC_RXTCPERROCT 0x027c /* RX TCP error octets */
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#define GMAC_MMC_RXICMPERROCT 0x0280 /* RX ICMP error octets */
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#define GMAC_MMC_CTRL_FHP __BIT(5) /* Full-Half preset */
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#define GMAC_MMC_CTRL_CP __BIT(4) /* Counters preset */
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#define GMAC_MMC_CTRL_MCF __BIT(3) /* MMC counter freeze */
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#define GMAC_MMC_CTRL_ROR __BIT(2) /* reset on read */
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#define GMAC_MMC_CTRL_CSR __BIT(1) /* Counter stop rollover */
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#define GMAC_MMC_CTRL_CR __BIT(0) /* Counters reset */
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#define AWIN_GMAC_DMA_BUSMODE 0x1000
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#define AWIN_GMAC_DMA_TXPOLL 0x1004
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#define AWIN_GMAC_DMA_RXPOLL 0x1008
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#define AWIN_GMAC_DMA_RX_ADDR 0x100c
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#define AWIN_GMAC_DMA_TX_ADDR 0x1010
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#define AWIN_GMAC_DMA_STATUS 0x1014
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#define AWIN_GMAC_DMA_OPMODE 0x1018
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#define AWIN_GMAC_DMA_INTENABLE 0x101c
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#define AWIN_GMAC_DMA_CUR_TX_DESC 0x1048
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#define AWIN_GMAC_DMA_CUR_RX_DESC 0x104c
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#define AWIN_GMAC_DMA_CUR_TX_BUFADDR 0x1050
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#define AWIN_GMAC_DMA_CUR_RX_BUFADDR 0x1054
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#define AWIN_GMAC_DMA_HWFEATURES 0x1058 /* not always implemented? */
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#define GMAC_MII_PHY_SHIFT 11
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#define GMAC_MII_PHY_MASK __BITS(15,11)
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#define GMAC_MII_REG_SHIFT 6
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#define GMAC_MII_REG_MASK __BITS(10,6)
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#define GMAC_MII_BUSY __BIT(0)
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#define GMAC_MII_WRITE __BIT(1)
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#define GMAC_MII_CLK_60_100M_DIV42 0x0
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#define GMAC_MII_CLK_100_150M_DIV62 0x1
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#define GMAC_MII_CLK_25_35M_DIV16 0x2
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#define GMAC_MII_CLK_35_60M_DIV26 0x3
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#define GMAC_MII_CLK_150_250M_DIV102 0x4
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#define GMAC_MII_CLK_250_300M_DIV124 0x5
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#define GMAC_MII_CLK_DIV4 0x8
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#define GMAC_MII_CLK_DIV6 0x9
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#define GMAC_MII_CLK_DIV8 0xa
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#define GMAC_MII_CLK_DIV10 0xb
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#define GMAC_MII_CLK_DIV12 0xc
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#define GMAC_MII_CLK_DIV14 0xd
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#define GMAC_MII_CLK_DIV16 0xe
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#define GMAC_MII_CLK_DIV18 0xf
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#define GMAC_MII_CLKMASK __BITS(5,2)
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#define GMAC_BUSMODE_4PBL __BIT(24)
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#define GMAC_BUSMODE_RPBL __BITS(22,17)
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#define GMAC_BUSMODE_FIXEDBURST __BIT(16)
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#define GMAC_BUSMODE_PRIORXTX __BITS(15,14)
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#define GMAC_BUSMODE_PRIORXTX_41 3
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#define GMAC_BUSMODE_PRIORXTX_31 2
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#define GMAC_BUSMODE_PRIORXTX_21 1
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#define GMAC_BUSMODE_PRIORXTX_11 0
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#define GMAC_BUSMODE_PBL __BITS(13,8) /* possible DMA
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burst len */
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#define GMAC_BUSMODE_RESET __BIT(0)
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#define AWIN_GMAC_MRCOIS __BIT(7) /* MMC RX csum offload intr */
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#define AWIN_GMAC_MTIS __BIT(6) /* MMC TX interrupt */
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#define AWIN_GMAC_MRIS __BIT(3) /* MMC RX interrupt */
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#define AWIN_GMAC_MIS __BIT(4) /* MMC interrupt */
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#define AWIN_GMAC_PIS __BIT(3) /* PMT interrupt */
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#define AWIN_GMAC_MII_IRQ __BIT(0) /* RGMII interrupt */
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#define GMAC_DMA_OP_DISABLECSDROP __BIT(26) /* disable dropping of
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frames with TCP/IP
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checksum errors */
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#define GMAC_DMA_OP_RXSTOREFORWARD __BIT(25) /* start RX when a
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full frame is available */
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#define GMAC_DMA_OP_DISABLERXFLUSH __BIT(24) /* Do not drop frames
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when out of RX descr. */
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#define GMAC_DMA_OP_TXSTOREFORWARD __BIT(21) /* start TX when a
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full frame is available */
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#define GMAC_DMA_OP_FLUSHTX __BIT(20) /* flush TX fifo */
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#define GMAC_DMA_OP_TTC __BITS(16,14) /* TX thresh control */
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#define GMAC_DMA_OP_TXSTART __BIT(13) /* start TX DMA engine */
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#define GMAC_DMA_OP_RTC __BITS(4,3) /* RX thres control */
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#define GMAC_DMA_OP_RXSTART __BIT(1) /* start RX DMA engine */
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#define GMAC_DMA_INT_MMC __BIT(27) /* MMC interrupt */
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#define GMAC_DMA_INT_NIE __BIT(16) /* Normal/Summary */
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#define GMAC_DMA_INT_AIE __BIT(15) /* Abnormal/Summary */
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#define GMAC_DMA_INT_ERE __BIT(14) /* Early receive */
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#define GMAC_DMA_INT_FBE __BIT(13) /* Fatal bus error */
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#define GMAC_DMA_INT_ETE __BIT(10) /* Early transmit */
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#define GMAC_DMA_INT_RWE __BIT(9) /* Receive watchdog */
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#define GMAC_DMA_INT_RSE __BIT(8) /* Receive stopped */
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#define GMAC_DMA_INT_RUE __BIT(7) /* Receive buffer unavail. */
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#define GMAC_DMA_INT_RIE __BIT(6) /* Receive interrupt */
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#define GMAC_DMA_INT_UNE __BIT(5) /* Tx underflow */
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#define GMAC_DMA_INT_OVE __BIT(4) /* Receive overflow */
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#define GMAC_DMA_INT_TJE __BIT(3) /* Transmit jabber */
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#define GMAC_DMA_INT_TUE __BIT(2) /* Transmit buffer unavail. */
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#define GMAC_DMA_INT_TSE __BIT(1) /* Transmit stopped */
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#define GMAC_DMA_INT_TIE __BIT(0) /* Transmit interrupt */
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#define GMAC_DMA_INT_MASK __BITS(0,16) /* all possible intr bits */
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#define GMAC_DMA_FEAT_ENHANCED_DESC __BIT(24)
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#define GMAC_DMA_FEAT_RMON __BIT(11) /* MMC */
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struct dwc_gmac_dev_dmadesc {
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uint32_t ddesc_status0; /* Status / TDES0 */
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/* both: */
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#define DDESC_STATUS_OWNEDBYDEV __BIT(31)
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/* for RX descriptors */
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#define DDESC_STATUS_DAFILTERFAIL __BIT(30)
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#define DDESC_STATUS_FRMLENMSK __BITS(29,16)
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#define DDESC_STATUS_FRMLENSHIFT 16
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#define DDESC_STATUS_RXERROR __BIT(15)
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#define DDESC_STATUS_RXTRUNCATED __BIT(14)
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#define DDESC_STATUS_SAFILTERFAIL __BIT(13)
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#define DDESC_STATUS_RXIPC_GIANTFRAME __BIT(12)
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#define DDESC_STATUS_RXDAMAGED __BIT(11)
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#define DDESC_STATUS_RXVLANTAG __BIT(10)
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#define DDESC_STATUS_RXFIRST __BIT(9)
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#define DDESC_STATUS_RXLAST __BIT(8)
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#define DDESC_STATUS_RXIPC_GIANT __BIT(7)
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#define DDESC_STATUS_RXCOLLISION __BIT(6)
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#define DDESC_STATUS_RXFRAMEETHER __BIT(5)
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#define DDESC_STATUS_RXWATCHDOG __BIT(4)
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#define DDESC_STATUS_RXMIIERROR __BIT(3)
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#define DDESC_STATUS_RXDRIBBLING __BIT(2)
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#define DDESC_STATUS_RXCRC __BIT(1)
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uint32_t ddesc_cntl1; /* Control / TDES1 */
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/* for TX descriptors */
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#define DDESC_CNTL_TXINT __BIT(31)
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#define DDESC_CNTL_TXLAST __BIT(30)
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#define DDESC_CNTL_TXFIRST __BIT(29)
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#define DDESC_CNTL_TXCHECKINSCTRL __BITS(27,28)
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#define DDESC_TXCHECK_DISABLED 0
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#define DDESC_TXCHECK_IP 1
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#define DDESC_TXCHECK_IP_NO_PSE 2
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#define DDESC_TXCHECK_FULL 3
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#define DDESC_CNTL_TXCRCDIS __BIT(26)
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#define DDESC_CNTL_TXRINGEND __BIT(25)
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#define DDESC_CNTL_TXCHAIN __BIT(24)
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#define DDESC_CNTL_TXDISPAD __BIT(23)
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/* for RX descriptors */
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#define DDESC_CNTL_RXINTDIS __BIT(31)
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#define DDESC_CNTL_RXRINGEND __BIT(25)
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#define DDESC_CNTL_RXCHAIN __BIT(24)
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/* both */
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#define DDESC_CNTL_SIZE1MASK __BITS(10,0)
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#define DDESC_CNTL_SIZE1SHIFT 0
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#define DDESC_CNTL_SIZE2MASK __BITS(21,11)
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#define DDESC_CNTL_SIZE2SHIFT 11
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uint32_t ddesc_data; /* pointer to buffer data */
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uint32_t ddesc_next; /* link to next descriptor */
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};
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/* Common to enhanced descriptors */
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#define DDESC_DES0_OWN __BIT(31)
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#define DDESC_DES1_SIZE2MASK __BITS(28,16)
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#define DDESC_DES1_SIZE1MASK __BITS(12,0)
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/* For enhanced TX descriptors */
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#define DDESC_TDES0_IC __BIT(30)
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#define DDESC_TDES0_LS __BIT(29)
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#define DDESC_TDES0_FS __BIT(28)
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#define DDESC_TDES0_TCH __BIT(20)
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/* For enhanced RX descriptors */
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#define DDESC_RDES0_FL __BITS(29,16)
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#define DDESC_RDES0_ES __BIT(15)
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#define DDESC_RDES0_LE __BIT(12)
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#define DDESC_RDES1_RCH __BIT(14)
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