141 lines
5.1 KiB
C
141 lines
5.1 KiB
C
/* $NetBSD: ibm82660reg.h,v 1.3 2008/06/14 12:01:28 mjf Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tim Rightnour
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_IBM82660REG_H_
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#define _DEV_IC_IBM82660REG_H_
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/* Register definitions for the IBM 82660 PCI Bridge Controller.
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* Also known as a Lanai/Kauai.
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*/
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/* Memmory Bank Starting Addresses */
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#define IBM_82660_MEM_BANK0_START 0x80
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#define IBM_82660_MEM_BANK1_START 0x81
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#define IBM_82660_MEM_BANK2_START 0x82
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#define IBM_82660_MEM_BANK3_START 0x83
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#define IBM_82660_MEM_BANK4_START 0x84
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#define IBM_82660_MEM_BANK5_START 0x85
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#define IBM_82660_MEM_BANK6_START 0x86
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#define IBM_82660_MEM_BANK7_START 0x87
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/* Memory Bank Extended Starting Addresses */
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#define IBM_82660_MEM_BANK0_EXTSTART 0x88
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#define IBM_82660_MEM_BANK1_EXTSTART 0x89
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#define IBM_82660_MEM_BANK2_EXTSTART 0x8A
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#define IBM_82660_MEM_BANK3_EXTSTART 0x8B
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#define IBM_82660_MEM_BANK4_EXTSTART 0x8C
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#define IBM_82660_MEM_BANK5_EXTSTART 0x8D
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#define IBM_82660_MEM_BANK6_EXTSTART 0x8E
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#define IBM_82660_MEM_BANK7_EXTSTART 0x8F
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/* Memory Bank Ending Addresses */
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#define IBM_82660_MEM_BANK0_END 0x90
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#define IBM_82660_MEM_BANK1_END 0x91
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#define IBM_82660_MEM_BANK2_END 0x92
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#define IBM_82660_MEM_BANK3_END 0x93
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#define IBM_82660_MEM_BANK4_END 0x94
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#define IBM_82660_MEM_BANK5_END 0x95
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#define IBM_82660_MEM_BANK6_END 0x96
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#define IBM_82660_MEM_BANK7_END 0x97
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/*
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* Helper functions for working with the Memory Bank
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* Start/End Address registers.
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*/
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#define IBM_82660_BANK0_ADDR(x) ((x) & 0xFF)
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#define IBM_82660_BANK1_ADDR(x) (((x) & 0xFF00) >> 8)
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#define IBM_82660_BANK2_ADDR(x) (((x) & 0xFF0000) >> 16)
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#define IBM_82660_BANK3_ADDR(x) (((x) & 0xFF000000) >> 24)
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/* Memory Bank Extended Ending Addresses */
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#define IBM_82660_MEM_BANK0_EXTEND 0x98
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#define IBM_82660_MEM_BANK1_EXTEND 0x99
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#define IBM_82660_MEM_BANK2_EXTEND 0x9A
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#define IBM_82660_MEM_BANK3_EXTEND 0x9B
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#define IBM_82660_MEM_BANK4_EXTEND 0x9C
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#define IBM_82660_MEM_BANK5_EXTEND 0x9D
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#define IBM_82660_MEM_BANK6_EXTEND 0x9E
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#define IBM_82660_MEM_BANK7_EXTEND 0x9F
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#define IBM_82660_MEM_BANK_ENABLE 0xA0
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#define IBM_82660_MEM_BANK0_ENABLED 0x01
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#define IBM_82660_MEM_BANK1_ENABLED 0x02
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#define IBM_82660_MEM_BANK2_ENABLED 0x04
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#define IBM_82660_MEM_BANK3_ENABLED 0x08
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#define IBM_82660_MEM_TIMING_1 0xA1
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#define IBM_82660_MEM_TIMING_2 0xA2
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/* Memory Bank Addressing Modes */
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#define IBM_82660_MEM_BANK01_ADDR_MODE 0xA4 /* Bank 0 and 1 */
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#define IBM_82660_MEM_BANK23_ADDR_MODE 0xA5 /* Bank 2 and 3 */
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#define IBM_82660_MEM_BANK45_ADDR_MODE 0xA6 /* Bank 4 and 5 */
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#define IBM_82660_MEM_BANK67_ADDR_MODE 0xA7 /* Bank 6 and 7 */
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#define IBM_82660_CACHE_STATUS 0xB1
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#define IBM_82660_CACHE_STATUS_L1_EN 0x01
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#define IBM_82660_CACHE_STATUS_L2_EN 0x02
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#define IBM_82660_RAS_WATCHDOG_TIMER 0xB6
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#define IBM_82660_SINGLEBIT_ERR_CNTR 0xB8
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#define IBM_82660_SINGLEBIT_ERR_LEVEL 0xB9
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/* Bridge Options */
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#define IBM_82660_OPTIONS_1 0xBA
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#define IBM_82660_OPTIONS_1_MCP 0x01
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#define IBM_82660_OPTIONS_1_TEA 0x02
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#define IBM_82660_OPTIONS_1_ISA 0x04
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#define IBM_82660_OPTIONS_2 0xBB
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#define IBM_82660_ERR_ENABLE_1 0xC0
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#define IBM_82660_ERR_STATUS_1 0xC1
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#define IBM_82660_CPU_ERR_STATUS 0xC3
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#define IBM_82660_ERR_ENABLE_2 0xC4
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#define IBM_82660_ERR_STATUS_2 0xC5
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#define IBM_82660_PCI_ERR_STATUS 0xC7
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#define IBM_82660_OPTIONS_3 0xD4
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#define IBM_82660_OPTIONS_3_ECC 0x01
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#define IBM_82660_OPTIONS_3_DRAM 0x04
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#define IBM_82660_OPTIONS_3_SRAM 0x08
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#define IBM_82660_OPTIONS_3_SNOOP 0x80
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#define IBM_82660_SYSTEM_CTRL 0x81C
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#define IBM_82660_SYSTEM_CTRL_L2_EN 0x40
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#define IBM_82660_SYSTEM_CTRL_L2_MI 0x80
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#endif /* _DEV_IC_IBM82660REG_H_ */
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