414 lines
17 KiB
C
414 lines
17 KiB
C
/* $NetBSD: hifn7751reg.h,v 1.1 2000/10/12 02:59:59 itojun Exp $ */
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/* $OpenBSD: hifn7751reg.h,v 1.15 2000/09/21 13:34:58 jason Exp $ */
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/*
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* Invertex AEON / Hi/fn 7751 driver
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* Copyright (c) 1999 Invertex Inc. All rights reserved.
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* Copyright (c) 1999 Theo de Raadt
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* Copyright (c) 2000 Network Security Technologies, Inc.
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* http://www.netsec.net
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*
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* Please send any comments, feedback, bug-fixes, or feature requests to
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* software@invertex.com.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_PCI_HIFN7751REG_H__
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#define __DEV_PCI_HIFN7751REG_H__
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#include <machine/endian.h>
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/*
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* Some PCI configuration space offset defines. The names were made
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* identical to the names used by the Linux kernel.
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*/
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#define HIFN_BAR0 (PCI_MAPREG_START + 0) /* PUC register map */
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#define HIFN_BAR1 (PCI_MAPREG_START + 4) /* DMA register map */
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/*
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* Some configurable values for the driver
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*/
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#define HIFN_D_CMD_RSIZE 24
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#define HIFN_D_SRC_RSIZE 80
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#define HIFN_D_DST_RSIZE 80
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#define HIFN_D_RES_RSIZE 24
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/*
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* The values below should multiple of 4 -- and be large enough to handle
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* any command the driver implements.
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*
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* MAX_COMMAND = base command + mac command + encrypt command +
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* mac-key + des-iv + 3des-key
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* MAX_RESULT = base result + mac result + mac + encrypt result
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*
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*
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*/
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#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 8 + 24)
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#define HIFN_MAX_RESULT (8 + 4 + 20 + 4)
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/*
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* hifn_desc_t
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*
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* Holds an individual descriptor for any of the rings.
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*/
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typedef struct hifn_desc {
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volatile u_int32_t l; /* length and status bits */
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volatile u_int32_t p;
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} hifn_desc_t;
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/*
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* Masks for the "length" field of struct hifn_desc.
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*/
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#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */
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#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */
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#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */
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#define HIFN_D_OVER 0x08000000 /* overflow */
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#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */
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#define HIFN_D_JUMP 0x40000000 /* jump descriptor */
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#define HIFN_D_VALID 0x80000000 /* valid bit */
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/*
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* hifn_callback_t
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*
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* Type for callback function when dest data is ready.
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*/
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typedef void (*hifn_callback_t)(hifn_command_t *);
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/*
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* Data structure to hold all 4 rings and any other ring related data.
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*/
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struct hifn_dma {
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/*
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* Descriptor rings. We add +1 to the size to accomidate the
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* jump descriptor.
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*/
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struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1];
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struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1];
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struct hifn_desc dstr[HIFN_D_DST_RSIZE+1];
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struct hifn_desc resr[HIFN_D_RES_RSIZE+1];
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struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE];
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u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
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u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
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/*
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* Our current positions for insertion and removal from the desriptor
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* rings.
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*/
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int cmdi, srci, dsti, resi;
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volatile int cmdu, srcu, dstu, resu;
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int cmdk, srck, dstk, resk;
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};
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struct hifn_session {
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int hs_flags;
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u_int8_t hs_iv[HIFN_IV_LENGTH];
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};
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/*
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* Holds data specific to a single HIFN board.
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*/
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struct hifn_softc {
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struct device sc_dv; /* generic device */
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void * sc_ih; /* interrupt handler cookie */
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u_int32_t sc_drammodel; /* 1=dram, 0=sram */
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bus_space_handle_t sc_sh0, sc_sh1;
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bus_space_tag_t sc_st0, sc_st1;
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bus_dma_tag_t sc_dmat;
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struct hifn_dma *sc_dma;
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int32_t sc_cid;
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int sc_maxses;
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int sc_ramsize;
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struct hifn_session sc_sessions[2048];
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};
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/*
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* Processing Unit Registers (offset from BASEREG0)
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*/
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#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
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#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
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#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
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#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
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#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
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#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
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#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
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#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
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#define HIFN_0_SPACESIZE 0x20 /* Register space size */
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/* Processing Unit Control Register (HIFN_0_PUCTRL) */
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#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
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#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
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#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
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#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
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#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
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/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
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#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
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#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
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#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
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#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
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#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
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#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
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#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
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#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
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#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
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#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
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/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
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#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
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#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
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#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
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#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
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#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
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#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
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#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
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#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
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#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
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#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
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#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
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#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
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#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
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#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
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#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
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#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
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#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
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#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
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#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
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#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
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#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
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#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
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#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
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/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
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#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
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#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
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#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
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#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
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#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
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#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
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#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
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#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
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#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
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#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
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/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
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#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
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#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
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#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
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#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
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#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
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#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
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#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
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#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
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#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
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#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
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#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
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#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
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#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
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#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
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#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
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#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
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#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
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/* FIFO Status Register (HIFN_0_FIFOSTAT) */
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#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
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#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
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/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
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#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
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/*
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* DMA Interface Registers (offset from BASEREG1)
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*/
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#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
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#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
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#define HIFN_1_DMA_RRAR 0x2c /* DMA Resultt Ring Address */
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#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
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#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
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#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
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#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
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#define HIFN_1_REVID 0x98 /* Revision ID */
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/* DMA Status and Control Register (HIFN_1_DMA_CSR) */
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#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
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#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
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#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
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#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
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#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
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#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
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#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
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#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
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#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
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#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
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#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
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#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
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#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
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#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
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#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
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#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
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#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
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#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
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#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
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#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
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#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
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#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
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#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
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#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
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#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
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#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
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#define HIFN_DMACSR_S_OVER 0x00000200 /* Source Ring Overflow */
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#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
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#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
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#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
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#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
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#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
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#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
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#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
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#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
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#define HIFN_DMACSR_C_EIRQ 0x00000001 /* Command Ring Engine IRQ */
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/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
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#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
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#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
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#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
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#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
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#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
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#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
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#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
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#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
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#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
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#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
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#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
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#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
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#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
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#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
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#define HIFN_DMAIER_S_OVER 0x00000200 /* Source Ring Overflow */
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#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
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#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
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#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
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#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
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#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
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/* DMA Configuration Register (HIFN_1_DMA_CNFG) */
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#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
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#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
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#define HIFN_DMACNFG_UNLOCK 0x00000800
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#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
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#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
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#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
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#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
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#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
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#define WRITE_REG_0(sc,reg,val) \
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bus_space_write_4((sc)->sc_st0, (sc)->sc_sh0, reg, val)
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#define READ_REG_0(sc,reg) \
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bus_space_read_4((sc)->sc_st0, (sc)->sc_sh0, reg)
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/*
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* Register offsets in register set 1
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*/
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#define HIFN_UNLOCK_SECRET1 0xf4
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#define HIFN_UNLOCK_SECRET2 0xfc
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#define WRITE_REG_1(sc,reg,val) \
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bus_space_write_4((sc)->sc_st1, (sc)->sc_sh1, reg, val)
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#define READ_REG_1(sc,reg) \
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bus_space_read_4((sc)->sc_st1, (sc)->sc_sh1, reg)
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/*********************************************************************
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* Structs for board commands
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*
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*********************************************************************/
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/*
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* Structure to help build up the command data structure.
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*/
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typedef struct hifn_base_command {
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volatile u_int16_t masks;
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volatile u_int16_t session_num;
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volatile u_int16_t total_source_count;
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volatile u_int16_t total_dest_count;
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} hifn_base_command_t;
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#define HIFN_BASE_CMD_MAC (0x1 << 10)
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#define HIFN_BASE_CMD_CRYPT (0x1 << 11)
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#define HIFN_BASE_CMD_DECODE (0x1 << 13)
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/*
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* Structure to help build up the command data structure.
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*/
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typedef struct hifn_crypt_command {
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volatile u_int16_t masks;
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volatile u_int16_t header_skip;
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volatile u_int32_t source_count;
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} hifn_crypt_command_t;
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#define HIFN_CRYPT_CMD_ALG_MASK (0x3 << 0)
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#define HIFN_CRYPT_CMD_ALG_DES (0x0 << 0)
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#define HIFN_CRYPT_CMD_ALG_3DES (0x1 << 0)
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#define HIFN_CRYPT_CMD_MODE_CBC (0x1 << 3)
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#define HIFN_CRYPT_CMD_NEW_KEY (0x1 << 11)
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#define HIFN_CRYPT_CMD_NEW_IV (0x1 << 12)
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/*
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* Structure to help build up the command data structure.
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*/
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typedef struct hifn_mac_command {
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volatile u_int16_t masks;
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volatile u_int16_t header_skip;
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volatile u_int32_t source_count;
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} hifn_mac_command_t;
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#define HIFN_MAC_CMD_ALG_MD5 (0x1 << 0)
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#define HIFN_MAC_CMD_ALG_SHA1 (0x0 << 0)
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#define HIFN_MAC_CMD_MODE_HMAC (0x0 << 2)
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#define HIFN_MAC_CMD_TRUNC (0x1 << 4)
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#define HIFN_MAC_CMD_RESULT (0x1 << 5)
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#define HIFN_MAC_CMD_APPEND (0x1 << 6)
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|
/*
|
|
* MAC POS IPSec initiates authentication after encryption on encodes
|
|
* and before decryption on decodes.
|
|
*/
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|
#define HIFN_MAC_CMD_POS_IPSEC (0x2 << 8)
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|
#define HIFN_MAC_CMD_NEW_KEY (0x1 << 11)
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|
|
|
/*
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|
* The poll frequency and poll scalar defines are unshifted values used
|
|
* to set fields in the DMA Configuration Register.
|
|
*/
|
|
#ifndef HIFN_POLL_FREQUENCY
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#define HIFN_POLL_FREQUENCY 0x1
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#endif
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|
|
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#ifndef HIFN_POLL_SCALAR
|
|
#define HIFN_POLL_SCALAR 0x0
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|
#endif
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|
|
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#endif /* __DEV_PCI_HIFN7751REG_H__ */
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