215 lines
6.0 KiB
C
215 lines
6.0 KiB
C
/* $NetBSD: intr.h,v 1.24 2006/12/21 15:55:22 yamt Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _BEBOX_INTR_H_
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#define _BEBOX_INTR_H_
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/* Interrupt priority `levels'. */
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#define IPL_NONE 9 /* nothing */
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#define IPL_SOFTCLOCK 8 /* software clock interrupt */
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#define IPL_SOFTNET 7 /* software network interrupt */
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#define IPL_BIO 6 /* block I/O */
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#define IPL_NET 5 /* network */
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#define IPL_SOFTSERIAL 4 /* software serial interrupt */
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#define IPL_TTY 3 /* terminal */
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#define IPL_LPT IPL_TTY
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#define IPL_VM 3 /* memory allocation */
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#define IPL_AUDIO 2 /* audio */
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#define IPL_CLOCK 1 /* clock */
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#define IPL_STATCLOCK IPL_CLOCK
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#define IPL_HIGH 1 /* everything */
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#define IPL_SCHED IPL_HIGH
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#define IPL_LOCK IPL_HIGH
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#define IPL_SERIAL 0 /* serial */
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#define NIPL 10
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#ifndef _LOCORE
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#define CLKF_BASEPRI(frame) ((frame)->pri == 0)
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/*
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* Interrupt handler chains. intr_establish() inserts a handler into
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* the list. The handler is called with its (single) argument.
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*/
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struct intrhand {
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int (*ih_fun) __P((void *));
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void *ih_arg;
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u_long ih_count;
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struct intrhand *ih_next;
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int ih_level;
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int ih_irq;
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};
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void do_pending_int __P((void));
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void ext_intr __P((void));
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void *intr_establish __P((int, int, int, int (*)(void *), void *));
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void intr_disestablish __P((void *));
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void intr_calculatemasks __P((void));
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int isa_intr __P((void));
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void isa_intr_mask __P((int));
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void isa_intr_clr __P((int));
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void enable_intr __P((void));
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void disable_intr __P((void));
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static __inline int splraise __P((int));
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static __inline int spllower __P((int));
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static __inline void splx __P((int));
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static __inline void set_sint __P((int));
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extern volatile int cpl, ipending, astpending, tickspending;
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extern int imask[];
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extern long intrcnt[];
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/*
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* Reorder protection in the following inline functions is
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* achieved with the "eieio" instruction which the assembler
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* seems to detect and then doesn't move instructions past....
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*/
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static __inline int
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splraise(newcpl)
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int newcpl;
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{
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int oldcpl;
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__asm volatile("sync; eieio\n"); /* don't reorder.... */
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oldcpl = cpl;
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cpl = oldcpl | newcpl;
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__asm volatile("sync; eieio\n"); /* reorder protect */
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return(oldcpl);
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}
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static __inline void
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splx(newcpl)
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int newcpl;
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{
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__asm volatile("sync; eieio\n"); /* reorder protect */
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cpl = newcpl;
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if(ipending & ~newcpl)
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do_pending_int();
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__asm volatile("sync; eieio\n"); /* reorder protect */
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}
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static __inline int
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spllower(newcpl)
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int newcpl;
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{
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int oldcpl;
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__asm volatile("sync; eieio\n"); /* reorder protect */
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oldcpl = cpl;
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cpl = newcpl;
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if(ipending & ~newcpl)
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do_pending_int();
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__asm volatile("sync; eieio\n"); /* reorder protect */
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return(oldcpl);
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}
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/* Following code should be implemented with lwarx/stwcx to avoid
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* the disable/enable. i need to read the manual once more.... */
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static __inline void
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set_sint(pending)
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int pending;
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{
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int msrsave;
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__asm ("mfmsr %0" : "=r"(msrsave));
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__asm volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE));
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ipending |= pending;
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__asm volatile ("mtmsr %0" :: "r"(msrsave));
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}
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#define ICU_LEN 32
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#define IRQ_SLAVE 2
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#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != IRQ_SLAVE)
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#define MOTHER_BOARD_REG 0x7ffff000
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#define CPU0_INT_MASK 0x0f0
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#define CPU1_INT_MASK 0x1f0
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#define INT_STATE_REG 0x2f0
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#define SINT_CLOCK 0x20000000
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#define SINT_NET 0x40000000
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#define SINT_SERIAL 0x80000000
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#define SPL_CLOCK 0x00000001
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#define SINT_MASK (SINT_CLOCK|SINT_NET|SINT_SERIAL)
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#define CNT_SINT_NET 29
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#define CNT_SINT_CLOCK 30
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#define CNT_SINT_SERIAL 31
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#define CNT_CLOCK 0
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#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
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#define setsoftclock() set_sint(SINT_CLOCK);
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#define setsoftnet() set_sint(SINT_NET);
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#define setsoftserial() set_sint(SINT_SERIAL);
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#define spl0() spllower(0)
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typedef int ipl_t;
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typedef struct {
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ipl_t _ipl;
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} ipl_cookie_t;
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static inline ipl_cookie_t
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makeiplcookie(ipl_t ipl)
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{
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return (ipl_cookie_t){._ipl = ipl};
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}
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static inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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return splraise(imask[icookie._ipl]);
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}
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#include <sys/spl.h>
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#endif /* !_LOCORE */
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#endif /* !_BEBOX_INTR_H_ */
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